![](http://datasheet.mmic.net.cn/280000/HD404369_datasheet_16064522/HD404369_9.png)
HD404369 Series
9
RAM Memory Map
A/D channel register (ACR)
A/D data register lower (ADRL)
A/D data register upper (ADRU)
A/D mode register 1 (AMR1)
A/D mode register 2 (AMR2)
$000
$000
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$040
$050
$020
$023
$024
$025
$026
$027
$028
$033
$034
$035
$036
$037
$038
$039
$00A
$00B
$00E
$00F
W
W
R/W
R/W
W
R/W
R/W
W
W
R/W
R/W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
W
$3C0
RAM-mapped registers
Memory registers (MR)
Stack (64 digits)
Interrupt control bits area
Port mode register A (PMRA)
Serial mode register (SMR)
Serial data register lower (SRL)
Serial data register upper (SRU)
Timer mode register A (TMA)
Timer mode register B1 (TMB1)
Timer B (TRBL/TWBL)
(TRBU/TWBU)
Miscellaneous register (MIS)
Timer mode register C (TMC)
Timer C (TRCL/TWCL)
(TRCU/TWCU)
Register flag area
Port R0 DCR (DCR0)
Port R1 DCR (DCR1)
Port R2 DCR (DCR2)
Port R3 DCR (DCR3)
Port R4 DCR (DCR4)
Port R5 DCR (DCR5)
Port R6 DCR (DCR6)
Port R7 DCR (DCR7)
Port R8 DCR (DCR8)
Port R9 DCR (DCR9)
Not used
1. Two registers are mapped
on the same area ($00A,
$00B, $00E, $00F).
2. Undefined.
Timer read register B lower (TRBL)
Timer read register B upper (TRBU)
Timer read register C lower (TRCL)
Timer read register C upper (TRCU)
Timer write register B lower (TWBL)
Timer write register B upper (TWBU)
Timer write register C lower (TWCL)
Timer write register C upper (TWCU)
R: Read only
W: Write only
R/W: Read/write
$200
Notes:
$016
$017
$018
$019
$01A
R
R
W
W
$3FF
W
W
W
W
W
W
Port mode register B (PMRB)
Port mode register C (PMRC)
Timer mode register B2 (TMB2)
System clock selection register 1 (SSR1)
System clock selection register 2 (SSR2)
Not used
DCR
DCR
DCR
DCR
$030
$031
$032
Not used
Not used
Not used
0000
0000
1000
0000
-000
0000
0000
Undefined
Undefined
0000
0000
*
2
/0000
Undefined
0000
0000
*
2
/0000
Undefined
0000
0000
0000
0000
0000
0000
0000
-000
0000
0000
0000
00-0
-000
000-
--00
*
1
Initial values
after reset
$03F
Data (432 digits)
0000
0000
0000
--00
Port D
0
–D
3
Port D
4
–D
7
Port D
8
–D
11
Port D
12
, D
13
W
W
W
W
(DCD0)
(DCD1)
(DCD2)
(DCD3)
$02C
$02D
$02E
$02F
Figure 2 RAM Memory Map