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參數(shù)資料
| 型號： | HD3-6409-9Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 9/14頁 |
| 文件大小： | 0K |
| 描述： | IC ENCODER-DECODER CMOS 20-PDIP |
| 標(biāo)準(zhǔn)包裝： | 180 |
| 類型： | 解碼器 |
| 應(yīng)用： | 光纖 |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 20-PDIP |
| 包裝： | 管件 |
4
FN2951.3
October 15, 2008
Encoder Operation
The encoder uses free running clocks at 1X and 2X the data
rate derived from the system clock lX for internal timing. CTS
is used to control the encoder outputs, ECLK, BOO and
BZO. A free running 1X ECLK is transmitted out of the
encoder to drive the external circuits which supply the NRZ
data to the MED at pin SD/CDS.
A low on CTS enables encoder outputs ECLK, BOO and
BZO, while a high on CTS forces BZO, BOO high and holds
ECLK low. When CTS goes from high to low
, a
synchronization sequence is transmitted out on BOO and
BZO. A synchronization sequence consists of eight
Manchester “0” bits followed by a command sync pulse.
A command sync pulse is a 3-bit wide pulse with the first 1
1/2 bits high followed by 1 1/2 bits low.
Serial NRZ data is
clocked into the encoder at SD/CDS on the high to low
transition of ECLK during the command sync pulse. The
NRZ data received is encoded into Manchester II data and
transmitted out on BOO and BZO following the command
sync pulse.
Following the synchronization sequence,
input data is encoded and transmitted out continuously
without parity check or word framing. The length of the data
block encoded is defined by CTS. Manchester data out is
inverted.
Decoder Operation
The decoder requires a single clock with a frequency 16X or
32X the desired data rate. The rate is selected on the speed
select with SS low producing a 16X clock and high a 32X
clock. For long data links the 32X mode should be used as
this permits a wider timing jitter margin. The internal
operation of the decoder utilizes a free running clock
synchronized with incoming data for its clocking.
The Manchester II encoded data can be presented to the
decoder in either of two ways. The Bipolar One and Bipolar
Zero inputs will accept data from differential inputs such as a
comparator sensed transformer coupled bus. The Unipolar
Data input can only accept noninverted Manchester II
encoded data i.e. Bipolar One Out through an inverter to
Unipolar Data Input. The decoder continuously monitors this
data input for valid sync pattern. Note that while the MED
encoder section can generate only a command sync pattern,
the decoder can recognize either a command or data sync
pattern. A data sync is a logically inverted command sync.
There is a three bit delay between UDI, BOl, or BZI input and
the decoded NRZ data transmitted out of SDO.
Control of the decoder outputs is provided by the RST pin.
When RST is low, SDO, DCLK and NVM are forced low.
When RST is high, SDO is transmitted out synchronously
with the recovered clock DCLK. The NVM output remains
low after a low to high transition on RST until a valid sync
pattern is received.
The decoded data at SDO is in NRZ format. DCLK is
provided so that the decoded bits can be shifted into an
external register on every high to low transition of this clock.
Three bit periods after an invalid Manchester bit is received
on UDI, or BOl, NVM goes low synchronously with the
questionable data output on SDO. FURTHER, THE
DECODER DOES NOT RE-ESTABLISH PROPER DATA
DECODING UNTIL ANOTHER SYNC PATTERN IS
RECOGNIZED.
1
2
3
4
CTS
ECLK
SD/CDS
BZO
BOO
tCE6
0
00
0
tCE5
SYNCHRONIZATION SEQUENCE
EIGHT “0’s”
COMMAND
SYNC
DON’T CARE
‘1’
‘0’
‘1’
‘0’ ‘1’
FIGURE 1. ENCODER OPERATION
1
2
3
4
HD-6409
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