參數(shù)資料
型號(hào): HCPL-316J
英文描述: 2.0 Amp Gate Drive Optocoupler with Integrated (V CE ) Desaturation Detection and Fault Status Feedback(帶集成不飽和檢測(cè)和誤差反饋的2.0 Amp門驅(qū)動(dòng)耦合器)
中文描述: 2.0安培門極驅(qū)動(dòng)光電耦合器與集成(五長(zhǎng)官)飽和檢測(cè)與故障狀態(tài)反饋(帶集成不飽和檢測(cè)和誤差反饋的2.0安培門驅(qū)動(dòng)耦合器)
文件頁(yè)數(shù): 23/32頁(yè)
文件大?。?/td> 503K
代理商: HCPL-316J
23
Behavioral Circuit
Schematic
The functional behavior of the
HCPL-316J is represented by the
logic diagram in Figure 64 which
fully describes the interaction and
sequence of internal and external
signals in the HCPL-316J.
Input IC
In the normal switching mode, no
output fault has been detected,
and the low state of the fault
latch allows the input signals to
control the signal LED. The fault
output is in the open-collector
state, and the state of the Reset
pin does not affect the control of
the IGBT gate. When a fault is
detected, the FAULT output and
Figure 64. Behavioral Circuit Schematic.
signal input are both latched. The
fault output changes to an active
low state, and the signal LED is
forced off (output LOW). The
latched condition will persist until
the Reset pin is pulled low.
Output IC
Three internal signals control the
state of the driver output: the
state of the signal LED, as well as
the UVLO and Fault signals. If no
fault on the IGBT collector is
detected, and the supply voltage
is above the UVLO threshold, the
LED signal will control the driver
output state. The driver stage
logic includes an interlock to
ensure that the pull-up and pull-
down devices in the output stage
are never on at the same time. If
an undervoltage condition is
detected, the output will be
actively pulled low by the 50x
DMOS device, regardless of the
LED state. If an IGBT
desaturation fault is detected
while the signal LED is on, the
Fault signal will latch in the high
state. The triple darlington AND
the 50x DMOS device are
disabled, and a smaller 1x DMOS
pull-down device is activated to
slowly discharge the IGBT gate.
When the output drops below two
volts, the 50x DMOS device again
turns on, clamping the IGBT gate
firmly to Vee. The Fault signal
remains latched in the high state
until the signal LED turns off.
V
IN+
(1)
V
IN–
(2)
V
CC1
(3)
GND (4)
FAULT (6)
RESET (5)
DELAY
R S
Q
FAULT
LED
12 V
+
V
CC2
(13)
7 V
+
DESAT (14)
V
E
(16)
250 μA
V
C
(12)
V
OUT
(11)
V
EE
(9,10)
50 x
1 x
F
UVLO
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