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參數(shù)資料
| 型號： | HC4094 |
| 廠商： | System Logic Semiconductor Co., Ltd. |
| 英文描述： | T-NPN-SI HIGH VLTG AMP |
| 中文描述： | 8位串行輸入鎖存移位寄存器與三態(tài)輸出（高性能硅柵CMOS） |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 315K |
| 代理商： | HC4094 |
SL74HC4094
S ystem Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
°
C to
-55
°
C
≤
85
°
C
≤
125
°
C
Unit
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 5)
2.0
4.5
6.0
6
30
35
5
25
28
4
20
23
MHz
t
, t
PHL
Maximum Propagation Delay, Clock to SQ
H
(Figures 1 and 5)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
t
PLH
, t
PHL
Maximum Propagation Delay, Clock to Q
A
-Q
H
(Figures 2 and 5)
2.0
4.5
6.0
195
40
33
245
50
42
295
60
50
ns
t
PLZ
, t
PHZ
Maximum Propagation Delay ,Output Enable to
Q
A
-Q
H
(Figures 3 and 6)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
t
PZL
, t
PZH
Maximum Propagation Delay ,Output Enable to
Q
A
-Q
H
(Figures 3 and 6)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
C
IN
Maximum Input Capacitance
-
10
10
10
pF
C
OUT
Maximum Three-State Output Capacitance
(Output in High-Impedance State), Q
A
-Q
H
-
15
15
15
pF
Power Dissipation Capacitance (Per Package)
Typical @25
°
C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic power
consumption: P
D
=C
PD
V
CC
2
f+I
CC
V
CC
300
pF
TIMING REQUIREMENTS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
°
C to
-55
°
C
≤
85
°
C
≤
125
°
C
Unit
t
su
Minimum Setup Time, Serial Data
Input A to Clock (Figure 4)
2.0
4.5
6.0
50
10
9.0
65
13
11
75
15
13
ns
t
h
Minimum Hold Time, Clock to Data
Input A (Figure 4)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
t
w
Minimum Pulse Width, Strobe (Figure
1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
t
r
, t
f
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
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