參數(shù)資料
型號: HC161
廠商: System Logic Semiconductor Co., Ltd.
元件分類: 通用總線功能
英文描述: Presettable Counters
中文描述: 可預(yù)置計數(shù)器
文件頁數(shù): 4/9頁
文件大?。?/td> 85K
代理商: HC161
SL74HC161
S ystem Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Guaranteed Limit
Symbol
Parameter
V
25
°
C to
-55
°
C
85
°
C
125
°
C
Unit
f
max
Maximum Clock Frequency (Figures 1,6)
2.0
4.5
6.0
6
30
35
5
24
28
4
20
24
MHz
t
PLH
Maximum Propagation Delay Clock to Q
2.0
4.5
6.0
120
20
16
160
23
20
200
28
22
ns
t
PHL
(Figures 1,6)
2.0
4.5
6.0
145
22
18
185
25
20
320
30
23
ns
t
PHL
Maximum Propagation Delay Reset to Q
(Figures 2 and 6)
2.0
4.5
6.0
145
20
17
185
22
19
220
25
21
ns
t
PLH
Maximum Propagation Delay Enable T to Ripple
Carry Out
2.0
4.5
6.0
110
16
14
150
18
15
190
20
17
ns
t
PHL
(Figures 3,6)
2.0
4.5
6.0
135
18
15
175
20
16
210
22
20
ns
t
PLH
Maximum Propagation Delay Clock to Ripple
2.0
4.5
6.0
120
22
18
160
27
22
200
30
25
ns
t
PHL
Carry Out (Figures 1,6)
2.0
4.5
6.0
145
22
20
185
28
24
220
35
28
ns
t
PHL
Maximum Propagation Delay Reset to Ripple Carry
Out (Figures 2,6)
2.0
4.5
6.0
155
22
18
190
26
22
230
30
25
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 6)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
C
IN
Maximum Input Capacitance
-
10
10
10
pF
Power Dissipation Capacitance (Per Gate)
Typical @25
°
C,V
CC
=5.0 V
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC
2
f+I
CC
V
CC
30
pF
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