參數(shù)資料
型號: HB52D48GB
廠商: Hitachi,Ltd.
英文描述: 32 MB Unbuffered SDRAM Micro DIMM(32MB 未緩沖同步DRAM DIMM)
中文描述: 32兆微型無緩沖SDRAM的內(nèi)存(32MB的未緩沖同步的DRAM內(nèi)存)
文件頁數(shù): 17/24頁
文件大小: 95K
代理商: HB52D48GB
HB52D48GB-F
17
AC Characteristics
(Ta = 0 to 65C, V
CC
= 3.3 V
±
0.3 V, V
SS
= 0 V)
HB52D48GB
-A6F/A6FL
-B6F/B6FL
Parameter
HITACHI
Symbol
PC100
Symbol Min
Max
Min
Max
Unit
Notes
System clock cycle time
(
CE
latency = 2)
(
CE
latency = 3)
t
CK
t
CK
t
CKH
t
CKL
Tclk
10
15
ns
1
Tclk
10
10
ns
CK high pulse width
Tch
3
3
ns
1
CK low pulse width
Tcl
3
3
ns
1
Access time from CK
(
CE
latency = 2)
(
CE
latency = 3)
t
AC
t
AC
t
OH
Tac
6
8
ns
1, 2
Tac
6
6
ns
Data-out hold time
Toh
3
3
ns
1, 2
CK to Data-out low impedance t
LZ
CK to Data-out high impedance t
HZ
Data-in setup time
2
2
ns
1, 2, 3
6
6
ns
1, 4
t
AS
, t
CS
,
t
DS
, t
CES
t
CESP
Tsi
2
2
ns
1, 5, 6
CKE setup time for power down
exit
Tpde
2
2
ns
1
Data-in hold time
t
AH
, t
CH
,
t
DH
, t
CEH
t
RC
Thi
1
1
ns
1, 5
Ref/Active to Ref/Active
command period
Trc
70
70
ns
1
Active to Precharge command
period
t
RAS
Tras
50
120000
50
120000
ns
1
Active command to column
command (same bank)
t
RCD
Trcd
20
20
ns
1
Precharge to active command
period
t
RP
Trp
20
20
ns
1
Write recovery or data-in to
precharge lead time
t
DPL
Tdpl
10
10
ns
1
Active (a) to Active (b)
command period
t
RRD
Trrd
20
20
ns
1
Transition time (rise and fall)
t
T
t
REF
1
5
1
5
ns
Refresh period
64
64
ms
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