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    參數(shù)資料
    型號(hào): HB28D032MM2
    廠商: Hitachi,Ltd.
    英文描述: MultiMediaCard 16 Mbyte/32 Mbyte/64 Mbyte/128 MByte
    中文描述: 多媒體16 Mbyte/32 Mbyte/64 Mbyte/128字節(jié)
    文件頁(yè)數(shù): 48/88頁(yè)
    文件大?。?/td> 329K
    代理商: HB28D032MM2
    HB28E016/D032/D064/B128MM2
    48
    Command Response Timings
    All timing diagrams use the following schematics and abbreviations:
    S: Start bit (= 0)
    T: Transmitter bit (Host = 1, Card = 0)
    P: One-cycle pull-up (= 1)
    E: End bit (= 1)
    Z: high impedance state (-> = 1)
    D: Data bits
    *: repeater
    CRC: Cyclic redundancy check bits (7 bits for command or response, 16 bits for block data)
    The difference between the P-bit and Z-bit is that a P-bit is actively driven to HIGH by the card
    respectively host output driver, while the Z-bit is driven to (respectively kept) HIGH by the pull-up
    resistors R
    CMD
    respectively R
    DAT
    . Actively driven P-bits are less sensitive to noise superposition. For the
    timing of these Hitachi MultiMediaCards, the following values are defined:
    Timing Values
    Value [clock cycles]
    Symbol
    Min
    Max
    Description
    N
    CR
    2
    64
    Number of cycles between command and
    response
    N
    ID
    5
    5
    Number of cycles between card identification
    or card operation conditions command and the
    corresponding response
    N
    AC
    2*
    1
    TAAC + NSAC*
    2
    Number of cycles between a command and
    the start of a related data block
    N
    RC
    8
    Number of cycles between the last response
    and a new command
    N
    CC
    8
    Number of cycles between two commands, if
    no response will be sent after the first
    command (e.g. broadcast)
    N
    WR
    2
    Number of cycles between a write command
    and the start of a related data block
    N
    ST
    2
    2
    Number of cycles between stop command and
    valid read / write data end
    Notes: 1. Refer to Chapter “Electrical Characteristics” for more details about the access time.
    2. Refer to Chapter “Time-out Condition”.
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