參數(shù)資料
型號: HA16116FP
廠商: Hitachi,Ltd.
元件分類: FPGA
英文描述: 1500000 SYSTEM GATE 1.5 VOLT FPGA
中文描述: 開關(guān)穩(wěn)壓器的斬波式直流/直流轉(zhuǎn)換器
文件頁數(shù): 11/34頁
文件大小: 250K
代理商: HA16116FP
HA16116FP/FPJ, HA16121FP/FPJ
11
+
+
PWM
comparator
C
T
R
1
R
2
DB
C
ST
V
To Vref
From UVL
E/O
DB
V
TH
V
E/O
V
DB
V
5k
TL
Off
On
t
ON
1.6 V typ
1.0 V typ
IN
V
GND
IN
V
GND
t
OFF
On
Off
T
PWM
pulse
output
Booster
channel
Step-down/
inverting
channel
V
IN
0.8V
Figure 3.1 Dead Band Duty Setting
3.2 Soft Start (SST) Setting (each channel)
When the power is turned on, the soft start function gradually raises V
DB
(refer to section 3.1), and the
PWM output pulse width gradually widens. This function is realized by adding a capacitor C
ST
to the DB
pin. The function is realized as follows.
In the figure 3.2, the DB pin is clamped internally at approximately 0.8 V, which is 0.2 V lower than the
triangle wave V
TL
= 1.0 V typ.
t
A
: Standby time until PWM pulse starts widening.
t
B
: Time during which SST is in effect.
During soft start, the DB pin voltage in the figure below is as expressed in the following equation.
V
SST
= V
DB
Here,
t
t
0.8
T
1
e
,
t
SST
= t
A
+ t
B
t
0.8
=
T ln
1
,
T = C
ST
(R
1
// R
2
)
0.8
V
DB
How to select values: If the soft start time t
SST
is too short, the DC/DC converter output voltage will tend to
overshoot. To prevent this, set t
SST
to a few tens of ms or above.
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