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參數(shù)資料
| 型號： | HA16108P |
| 廠商： | Hitachi,Ltd. |
| 元件分類： | FPGA |
| 英文描述： | 1500000 SYSTEM GATE 1.5 VOLT FPGA |
| 中文描述： | PWM開關(guān)穩(wěn)壓器的高性能電壓模式控制 |
| 文件頁數(shù)： | 12/38頁 |
| 文件大小： | 170K |
| 代理商： | HA16108P |
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HA16107P/FP, HA16108P/FP
12
Timer Latch and ON/OFF Timer
The HA16107 has a built-in timer-latch function. The HA16108 has a built-in ON/OFF timer function.
The timer-latch function is an overvoltage protection function that combines latched shutdown of PWM
output with a timer function to vary the time until latched shutdown occurs according to the overcurrent
value. A dedicated voltage detection pin is provided in addition to Vref overvoltage protection.
The ON/OFF timer function is equivalent to the above timer-latch function without the latch. If
overcurrent is detected continuously, PWM output shuts down temporarily, then normal operation resumes.
This process repeats, temporary shutdown alternating with normal operation.
Both the timer-latch function in the HA16107 and the ON/OFF function in the HA16108 wait for an
interval after overcurrent detection before shutting down PWM output. The interval is determined by
capacitor C
TM
and the value of the charge/discharge current supplied internally from the IC. Normal
operation therefore continues if a single overcurrent spike is detected, while if continuous overcurrent is
detected, the current and voltage droop curves for the secondary-side output have sharp characteristics.
1. Use of Timer-Latch Pin (HA16107)
Timer-Latch Usage
See external circuit 1 in the following diagram. Under continuous overcurrent, the CML switch turns
on, charging C
TM
with 12
μ
A. PWM output shuts down when the voltage at pin 15 exceeds 7 V.
Overvoltage Protection Usage
See external circuit 2 in the diagram. This configuration is suitable when overvoltage is detected by an
OVP signal received through an optocoupler from the DC output on the secondary side of an AC/DC
converter. PWM output shuts down when the OVP signal allows the voltage at the TL pin to exceed 7
V. The shutdown is latched. V
IN
must go below approximately 6.5 V (V
INR2
) to release the latched
state.
C
TM
15
16
μ
A
4
μ
A
from CML
OVP with
latch timer
HA16107
V
IN
OVP signal
(from secondary)
External circuit 1
T
L
V
TH
Latch
(PWM output shuts down)
7.0 V
0 V
V
TL
A
B
t
OCL detected continuously
(activating pulse-by-pulse current limiter)
Path A is followed if the OCL input stops before V
is reached.
Path B is followed if OCL is detected continuously until the latch point is reached.
Notes: 1.
2.
3. The latch function is cleared when V
IN
goes below approximately 7.0 V.
External circuit 2
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