參數(shù)資料
型號(hào)： HA16108FP
廠商： Hitachi,Ltd.
元件分類： FPGA
英文描述： 1500000 SYSTEM GATE 1.5 VOLT FPGA
中文描述： PWM開(kāi)關(guān)穩(wěn)壓器的高性能電壓模式控制
文件頁(yè)數(shù)： 7/38頁(yè)
文件大小： 170K
代理商： HA16108FP
HA16107P/FP, HA16108P/FP
7
1. Timing in Normal Operation
Timing in these ICs is based on a triangular voltage waveform. The rising edge (leading edge) defines
the deadband time t
DB
. The falling edge (trailing edge) defines the ON-duty control band t
ON
. PWM
output is on in the area within t
ON
that is bounded above by the triangle wave V
CT
and error output V
E/O
.
The following pin outputs are related to PWM control:
C
T
(pin 7): triangle-wave voltage output
E/O (pin 15): error output voltage
R
T2
(pin 8): ON-duty pulse output voltage
OUT (pin 2): PWM pulse output (for driving the gate of a power MOS FET)
2. Triangle Oscillator, Waveform and Frequency
The triangle oscillator in these ICs generates a triangular waveform by charging and discharging timing
capacitor C
T
with a constant current, as shown in the equivalent circuit. The C
T
charge current is:
I(C
Tchg
) = I
1
=V
REF
2V
BE
R
T1
The discharge current is:
I(C
Tdischg
) = 2I
2
I
1
, where I
2
=V
REF
2V
BE
R
T2
In these equations Vref (reference voltage) is typically 6.45 V, and V
BE
(base-emitter voltage of
internal transistors) is about 0.7 V.
The deadband time is:
C
T
×
R
T1
×
2V
V
REF
2V
BE
≈
0.4
×
C
T
×
R
T1
+ 0.8
μ
s
The ON-duty time is:
R
T2
2R
T1
R
T2
The 0.8
μ
s in these equations is a correction term for internal circuit delays.
The maximum ON-duty is
R
T2
2R
T1
The oscillating frequency is:
1
f
OSC
=
t
DB
1
Du max
1
0.8
×
C
T
×
R
T12
2R
T1
R
T2
When R
T1
= R
T2
, the maximum ON-duty is 50%, and:
1
0.8 C
T
R
T1
+ 0.8
μ
s
This approximation is fairly close, but it should be checked in-circuit.
+ 0.8
μ
s
t
DB
=
t
ON
= t
DB
×
Du max =
+ 0.8
μ
s
=
+ 0.8
μ
s
(Hz)
f
OSC
≈
(Hz)
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