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參數資料
| 型號： | GTL |
| 文件頁數： | 1/2頁 |
| 文件大小： | 101K |
| 代理商： | GTL |
October 1995
GTL Logic
K E Y
T
e
available in JEDEC
e
available in EIAJ
e
available in JEDEC and EIAJ
e
available in wide format
e
available in standard and
wide format
e
planned in standard;
available in wide format
e
T
e
w
T
w
Pw
&
e
military temperature range
e
military temperature range and MIL-STD-883
e
military temperature range, MIL-STD-883,
and SMD
e
military temperature range, MIL-STD-883,
SMD, MIL S
e
military temperature range and SMD
e
MIL-STD-883
e
SMD
e
MIL-STD-883 and SMD
e
MIL-STD-883, SMD, MIL S
e
MIL-STD-883, SMD, JAN B
e
MIL-STD-883 and JAN B
e
MIL-STD-883, JAN B, and JAN S
e
MIL-STD-883, SMD, JAN B, and JAN S
e
MIL-STD-883, SMD, JAN B, JAN S, and
RHA qualified as ‘‘R’’
Z
F
O
D
X
!
3
2
V
U
#
P
e
Planned
e
To Be Announced
TBA
CDIP
e
Ceramic Dual In-Line Package
e
Plastic Dual In-Line Package
e
Ceramic Flatpak
MQUAD
e
Metal Quad Flatpak
PQFP
e
Quad Flatpak
LCC
e
Ceramic Leadless Chip Carrier
SOIC
e
Small Outline Integrated Circuit
SSOP
e
Small Shrink Outline Package
QSOP
e
Quarter Size Outline Package
PPGA
e
Plastic Pin Grid Array
PDIP
FPAK
1
e
CDIP standard package 400-mil wide
e
Also in 600-mil wide DIP
e
300-mil wide
e
20-lead package
e
400-mil wide
2
3
4
5
Commercial package width standards:
8-, 14-, 16-lead SOIC
e
150-mil wide
20-, 24-, 28-lead SOIC
e
300-mil wide
8-, 14-, 16-, 20-, 24-lead PDIP
e
300-mil wide
28-lead PDIP
e
600-mil wide
1
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