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參數(shù)資料
| 型號： | GTL2003PW |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 電壓/頻率轉(zhuǎn)換 |
| 英文描述： | 8-bit bidirectional low voltage translator |
| 封裝： | GTL2003BQ<SOT764-1 (DHVQFN20)|<<http://www.nxp.com/packages/SOT764-1.html<1<Always Pb-free,;GTL2003PW<SOT360-1 (TSSOP20)|<<http://www.nxp.com/packages/SOT360-1.html<1& |
| 文件頁數(shù)： | 5/19頁 |
| 文件大?。?/td> | 113K |
| 代理商： | GTL2003PW |
GTL2003_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 27 July 2007
5 of 19
NXP Semiconductors
GTL2003
8-bit bidirectional low voltage translator
8.
Application design-in information
8.1 Bidirectional translation
For the bidirectional clamping configuration, higher voltage to lower voltage or lower
voltage to higher voltage, the GREF input must be connected to DREF and both pins
pulled to HIGH side V
CC
through a pull-up resistor (typically 200 k
). A filter capacitor on
DREF is recommended. The processor output can be totem pole or open-drain (pull-up
resistors may be required) and the chip set output can be totem pole or open-drain
(pull-up resistors are required to pull the Dn outputs to V
CC
). However, if either output is
totem pole, data must be unidirectional or the outputs must be 3-stateable and the outputs
must be controlled by some direction control mechanism to prevent HIGH-to-LOW
contentions in either direction. If both outputs are open-drain, no direction control is
needed. The opposite side of the reference transistor (SREF) is connected to the
processor core power supply voltage. When DREF is connected through a 200 k
resistor
to a 3.3 V to 5.5 V V
CC
supply and SREF is set between 1.0 V to (V
CC
1.5 V), the output
of each Sn has a maximum output voltage equal to SREF and the output of each Dn has
a maximum output voltage equal to V
CC
.
Typical bidirectional voltage translation.
Fig 4.
Bidirectional translation to multiple higher voltage levels such as an I
2
C-bus
application
GREF
DREF
002aac642
D1
D2
200 k
GTL2002
CHIPSET I/O
V
CC
5 V
totem pole or
open-drain I/O
GND
SREF
S1
S2
increase bit size
by using 8-bit GTL2003,
10-bit GTL2010,
or 22-bit GTL2000
D3
D4
CHIPSET I/O
V
CC
D5
Dn
3.3 V
S3
S4
S5
Sn
CPU I/O
V
CORE
1.8 V
1.5 V
1.2 V
1.0 V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GTL2005PW | Quad GTL-GTL+ to LVTTL-TTL bidirectional non-latched translator |
| GTL2006PW | 13-bit GTL--GTL-GTL+ to LVTTL translator |
| GTL2007PW | 12-bit GTL to LVTTL translator with power good control |
| GTL2008PW | 12-bit GTL to LVTTL translator with power good control and high-impedance LVTTL and GTL outputs |
| GTL2010BS | 10-bit bidirectional low voltage translator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GTL2003PW,112 | 功能描述:轉(zhuǎn)換 - 電壓電平 8-BIT GTL VOLTAGE RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| GTL2003PW,118 | 功能描述:轉(zhuǎn)換 - 電壓電平 8-BIT GTL VOLTAGE RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| GTL2003PW,118-CUT TAPE | 制造商:NXP 功能描述:GTL2003 Series I2C 8-Bit Bidirectional Low Voltage Translator - TSSOP - 20 |
| GTL2003PW-T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:NXP bidirectional low-voltage translators |
| GTL2004 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Quad GTL/GTL to LVTTL/TTL bidirectional latched translator |
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