參數(shù)資料
型號(hào): GS9090A
廠商: Gennum Corporation
英文描述: GS9090A GenLINX-R III 270Mb/s Deserializer for SDI
中文描述: GS9090A GenLINX - R的第三270Mb / s的SDI解串器
文件頁(yè)數(shù): 11/69頁(yè)
文件大小: 687K
代理商: GS9090A
GS9090A Preliminary Data Sheet
Proprietary and Confidential
34714 - 0
February 2006
11 of 69
51
FW_EN
Non
Synchronous
Input
CONTOL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Used to enable or disable the noise immune flywheel of the device.
When set HIGH, the internal flywheel is enabled. This flywheel is used
in the extraction of timing signals, the generation of TRS signals, the
automatic detection of video standards, and in manual switch line lock
handling.
When set LOW, the internal flywheel is disabled. Timing based TRS
errors will not be detected.
52
FIFO_EN
Non
Synchronous
Input
CONTOL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Used to enable / disable the internal FIFO.
When FIFO_EN is HIGH, the internal FIFO will be enabled. Data will be
clocked out of the device on the rising edge of the RD_CLK input pin if
the FIFO is in video mode or DVB-ASI mode.
When FIFO_EN is LOW, the internal FIFO is bypassed and parallel
data is clocked out on the rising edge of the PCLK output.
53
VCO_VDD
Analog
Input
Power
Power supply connection for Voltage-Controlled-Oscillator. Connect to
+1.8V DC.
54
LB_CONT
Analog
Input
CONTROL SIGNAL INPUT
Control voltage to fine-tune the loop bandwidth of the PLL.
55
VCO_GND
Analog
Input
Power
Ground connection for Voltage-Controlled-Oscillator. Connect to GND.
56
LF+
Analog
Input
Loop filter component connection. Connect to pin 1 (LF-) as shown in
Typical Application Circuit (Part B) on page 66
.
Center Pad
Power
Connect to GND following recommendations in
Recommended PCB
Footprint on page 68
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
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