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參數(shù)資料
| 型號(hào)： | GS9023ACFY |
| 廠商： | Gennum Corporation |
| 元件分類： | Codec |
| 英文描述： | GENLINX -TM II GS9023A Embedded Audio CODEC |
| 中文描述： | GENLINX -商標(biāo)二GS9023A嵌入式音頻編解碼器 |
| 文件頁數(shù)： | 8/37頁 |
| 文件大小： | 318K |
| 代理商： | GS9023ACFY |
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G
GENNUM CORPORATION
19795 - 6
2. DETAILED DESCRIPTION
The GS9023A has two main modes of operation: Multiplex
Mode and Demultiplex Mode. In Multiplex Mode, which is
selected by setting the DEMUX/MUX input pin LOW, digital
audio is embedded into a digital video stream. In
Demultiplex Mode, which is selected by setting the DEMUX/
MUX input pin HIGH, digital audio is extracted from a digital
video stream. Table 14 and Table 15 contain Host Interface
Register descriptions for the Multiplex and Demultiplex
Modes respectively.
2.1 MULTIPLEX MODE
2.1.1 Video Clock Input
A master video clock must be supplied to the PCLK pin
corresponding to the selected video standard. The
supported video input standards and corresponding clock
frequencies are listed in Table 1.
2.1.2 Video Data Input
The video data DIN[9:0] is clocked into the GS9023A on the
rising edge of PCLK. The video clock frequency must
correspond to the video input standard selected. This is
done via the “VSEL” bit of Host Interface Register #0h.
When “VSEL” is LOW, the video input standard is selected
by the VM[2:0] and TRS input pins. When “VSEL” is HIGH,
the video input standard is selected by the “VMOD[2:0]”
and “D2_TRS” bits in Host Interface Register #0h. The
supported video input standards are listed in Table 1.
After the user has specified the video input standard via the
VM[2:0] and TRS pins or by setting Host Interface Register
#0h, the GS9023A performs video standard detection to
verify that the input video stream corresponds to the
selected standard. The LOCK output pin and the “LOCK”
bit of Host Interface Register #0h are then set HIGH if at
least one of the audio channel enable bits “CHACT(4-1)” of
Host Interface Register #1h is HIGH and the start of a video
frame is detected.
NOTE: The user must ensure that the video input format
correctly corresponds to the video format being provided to
the GS9023A. For 8-bit video operation, the "8BIT_SEL" bit
of the Host Interface Register #2h must be set HIGH.
TABLE 1 VIDEO INPUT FORMATS
VIDEO STANDARD
SERIAL DIGITAL
DATA RATE
(MBPS)
PCLK
FREQUENCY
(MHZ)
VM[2] OR
“VMOD[2]”
VM[1] OR
“VMOD[1]”
VM[0] OR
“VMOD[0]”
TRS OR
“D2_TRS”
525/D2 (SMPTE259M)
143
14.3
0
0
0
0
525/D2 (SMPTE244M)
143
14.3
0
0
0
1
525/D1
270
27.0
0
0
1
0
Reserved
-
-
0
0
1
1
525/16:9
360
36.0
0
1
0
0
Reserved
-
-
0
1
0
1
525/4:4:4:4 (System #1)
540
54.0
0
1
1
0
Reserved
-
-
0
1
1
1
625/D2 (with TRS)
177
17.7
1
0
0
0
625/D2 (without TRS)
177
17.7
1
0
0
1
625/D1
270
27.0
1
0
1
0
Reserved
-
-
1
0
1
1
625/16:9
360
36.0
1
1
0
0
Reserved
-
-
1
1
0
1
625/4:4:4:4 (System #2)
540
54.0
1
1
1
0
625/4:2:2P (System #4)
540
54.0
1
1
1
1
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| GS9023B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Embedded Audio CODEC |
| GS9023BCVE3 | 功能描述:IC AUDIO CODEC 100PIN TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| GS9023-CFY | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Embedded Audio CODEC |
| GS9024 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Automatic Cable Equalizer |
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