參數(shù)資料
型號: GS9023
廠商: Electronic Theatre Controls, Inc.
元件分類: Codec
英文描述: Embedded Audio CODEC
中文描述: 嵌入式音頻編解碼器
文件頁數(shù): 16/33頁
文件大小: 301K
代理商: GS9023
GENNUM CORPORATION
522 - 45 - 05
16
G
The audio control packet delay word bits are defined as
follows:
e:
Indicates valid audio delay data when set HIGH.
Corresponds to the
ACDLY
bit of Host Interface Register
#Dh.
dela/b[25:0]:
The audio channel pair delay is programmed
in bits
DELA/B[25:0]
of Host Interface Register #Ah, #Bh,
#Ch and #Dh. DELA[25:0] corresponds to the delay for
channels 1 and 2.
DELB[25:0]
corresponds to the delay
for channels 3 and 4.
RSRV: Reserved.
The word is fixed at 200h and is
automatically generated by the GS9023.
CS: Checksum.
The checksum consists of nine bits. The
checksum is used to determine the validity of the words
data ID through user data. It is the sum of the nine least
significant bits of the words data ID through user data. The
checksum is automatically generated by the GS9023.
Arbitrary Data Packets
The GS9023 is capable of multiplexing arbitrary data
packets according to SMPTE 291M. Typically, this consists
of linear time code data (LTC), vertical interval time code
data (VITC) or other data which is multiplexed once per
field. The user must input the 9 LSBs starting from the
secondary data identification (SDID) word to the last user
data word (UDW) of the ancillary data packet containing
arbitrary data. The CS word and bit 10 of all words in the
packet are internally generated.
The arbitrary data packet data ID is configured in
PKTID[7:0]
of Host Interface Register #5h. To process
arbitrary data, the user must set the
PKON
bit of Host
Interface Register #1h. Also, the user must specify the line
number in
PKTLINE[7:0]
in Host Interface Register #9h.
This value corresponds to the line in video field 1 in which
the user wants the arbitrary data packet to be multiplexed.
The corresponding line in field 2 is automatically selected
for arbitrary data packet multiplexing. Arbitrary data is
typically multiplexed during the active portion of the line in
the vertical blanking interval (VBI). Care should be taken to
avoid selecting a line in the active picture. Table 11 lists
recommended multiplexing lines according to the video
standard.
NOTE: In field #1, the line number is offset by one from the
value configured in
PKTLINE[7:0]
.
Arbitrary data is input to the GS9023 as shown in Figure 9.
The data is stored in an internal arbitrary data packet buffer
which is cleared at the end of every field. Arbitrary data
must be written to the buffer before the line number
specified in
PKTLINE[7:0]
is reached in order for the
packet to be multiplexed. Data is input to the PKT[8:0] pins
and clocked in on the rising edge of PCLK. PKTEN must be
set HIGH one PCLK cycle before the data at the PKT[8:0]
inputs is valid. PKTEN must go LOW one PCLK cycle before
the last user data word (UDW) is input to the PKT[8:0]
inputs. Parity (bit 8) for each UDW can be enabled by
setting the
PKTPRTY
bit of Host Interface Register #8h to
HIGH. When
PKTPRTY
is HIGH, data input at PKT[8] is
overwritten by the parity bit.
Up to 255 words (253 UDWs + SDID + DC) can be input
and multiplexed once per field.
The arbitrary data packet structure as described in SMPTE
291M is shown in Figure 9.
TABLE 10: Audio Control Packet Delay Structure
BIT
DELx0
DELx1
DELx2
b9
not b8
not b8
not b8
b8
dela/b 7
dela/b 16
dela/b 25 (Sign)
b7
dela/b 6
dela/b 15
dela/b 24 (MSB)
b6
dela/b 5
dela/b 14
dela/b 23
b5
dela/b 4
dela/b 13
dela/b 22
b4
dela/b 3
dela/b 12
dela/b 21
b3
dela/b 2
dela/b 11
dela/b 20
b2
dela/b 1
dela/b 10
dela/b 19
b1
dela/b 0
(LSB)
dela/b 9
dela/b 18
b0
e
dela/b 8
dela/b 17
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