參數(shù)資料
型號(hào)： GS9021A
廠商： Gennum Corporation
英文描述： GENLINX -TM II GS9021A EDH Coprocessor
中文描述： GENLINX -商標(biāo)二GS9021A硬腦膜外血腫協(xié)處理器
文件頁(yè)數(shù)： 3/26頁(yè)
文件大?。?/td> 245K
代理商： GS9021A
19983 - 1
3 of 26
G
AC ELECTRICAL CHARACTERISTICS
V
DD
= 5.0V, T
A
= 0 to 70°C unless otherwise shown.
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
NOTES
Input Clock Frequency
-
-
54
MHz
Clock Pulse Width Low
t
PWL
7.4
-
-
ns
Clock Pulse Width High
t
PWH
7.4
-
-
ns
Input Setup Time
t
S
3
-
-
ns
1, 2
Input Hold Time
t
H
3
-
-
ns
1, 2
Output Delay Time
t
OD
with 10pF loading
-
-
15
ns
2
Output Hold Time
t
OH
with 10pF loading
5
-
-
ns
2
Output Setup Time
t
OS
with 10pF loading
3.5
-
-
ns
2,4
Flag Port Disable Time
t
FDIS
with 25pF loading
-
-
15
ns
Flag Port Enable Time
t
FEN
with 25pF loading
-
-
16
ns
I2C Clock Frequency
SCL
-
-
400
kHz
Host Interface Setup Time
t
HS
6
-
-
ns
Host Interface Hold Time
t
HH
6
-
-
ns
Host Interface Output
Enable Time
t
HEN
with 25pF loading
-
-
21
ns
Host Interface Output
Disable Time
t
HDIS
with 25pF loading
-
-
10
ns
Reset Time Pulse Width
t
RESET
100
-
-
ns
Device Latency
t
LAT
8
8
8
clks
3
NOTES
1. See section 1.2 for a list of signals synchronous and asynchronous to PCLKIN.
2. See Figures 1 and 2.
3. Latency is defined as the number of clock cycles between the time when the data is latched into the device and when the
corresponding output data is clocked into the next device as shown in Figure 3.
4) Based upon 54MHz clock (18.5ns). Output Setup Time = Clock Period - Output Delay Time
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