參數(shù)資料
型號: GS882V36BGD-333I
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
中文描述: 256K X 36 CACHE SRAM, 4.5 ns, PBGA165
封裝: 13 X 15 MM, 1 MM PITCH, LEAD FREE, FBGA-165
文件頁數(shù): 25/36頁
文件大?。?/td> 732K
代理商: GS882V36BGD-333I
GS882V18/36BB/D-333/300/250/200
Rev: 1.02 3/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
25/36
2004, GSI Technology
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Die
Revision
Code
Not Used
I/O
Configuration
GSI Technology
JEDEC Vendor
ID Code
P
0
1
1
1
Bit #
x72
x36
x18
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
X
X
X
X
0
0
0
0
0
0
0
0
0
0
X
X
X
X
0
0
0
0
0
0
0
0
0
0
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
0 1 1 0 1 1 0 0 1
Instruction Register
ID Code Register
·
31 30 29
Boundary Scan Register
0
1
2
0
· · ·
1
2
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
1
·
1
0
·
·
·
·
·
·
·
·
·
Control Signals
·
相關(guān)PDF資料
PDF描述
GS882V37AB-225 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
GS882V37AB-225I 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
GS882V37AB-250 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
GS882V37AB-250I 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
GS882V37AD-200 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
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