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參數(shù)資料
| 型號： | GS881Z18BT-V |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 9Mb Pipelined and Flow Through Synchronous NBT SRAM |
| 中文描述： | 9MB的流水線和流量，通過同步唑的SRAM |
| 文件頁數(shù)： | 17/37頁 |
| 文件大小： | 773K |
| 代理商： | GS881Z18BT-V |
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GS881Z18/32/36B(T/D)-xxxV
Rev: 1.00 6/2006
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
17/37
2006, GSI Technology
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I
SB
2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I
SB
2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
tZZR
tZZH
tZZS
tKL
tKH
tKC
CK
ZZ
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipelinemode via the FT signal found
on Pin 14. Not all vendors offer this option, however most mark Pin 14 as V
DD
or V
DDQ
on pipelined parts and V
SS
on flow
through parts. GSI NBT SRAMs are fully compatible with these sockets.
Pin 66, a No Connect (NC) on GSI’s GS8160Z18/36 NBT SRAM, the Parity Error open drain output on GSI’s GS881Z18/36B
NBT SRAM, is often marked as a power pin on other vendor’s NBT compatible SRAMs. Specifically, it is marked V
DD
or V
DDQ
on pipelined parts and V
SS
on flow through parts. Users of GSI NBT devices who are not actually using the ByteSafe parity
feature may want to design the board site for the RAM with Pin 66 tied high through a 1k ohm resistor in Pipeline mode
applications or tied low in Flow Through mode applications in order to keep the option to use non-configurable devices open.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS881Z18CD-150I | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 9MBIT 512KX18 7.5NS/3.8NS 165FPBGA - Trays |
| GS881Z18CD-200 | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 9MBIT 512KX18 6.5NS/3NS 165FPBGA - Trays |
| GS881Z18CD-250 | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 9MBIT 512KX18 5.5NS/2.5NS 165FPBGA - Trays |
| GS881Z18CD-250I | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 9MBIT 512KX18 5.5NS/2.5NS 165FPBGA - Trays |
| GS881Z18CD-300 | 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 9MBIT 512KX18 5NS/2.5NS 165FPBGA - Trays |
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