參數(shù)資料
型號(hào): GS881E36BGT-250T
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 256K X 36 CACHE SRAM, 5.5 ns, PQFP100
封裝: ROHS COMPLIANT, TQFP-100
文件頁(yè)數(shù): 3/39頁(yè)
文件大?。?/td> 815K
代理商: GS881E36BGT-250T
GS881E18B(T/D)/GS881E32B(T/D)/GS881E36B(T/D)
Rev: 1.04a 3/2009
11/39
2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Note:
There is a are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so thosethis input pins can be
unconnected and the chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
BPR 1999.05.18
Mode Pin Functions
Mode Name
Pin Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
Single/Dual Cycle Deselect Control
SCD
L
Dual Cycle Deselect
H or NC
Single Cycle Deselect
FLXDrive Output Impedance Control
ZQ
L
High Drive (Low Impedance)
H or NC
Low Drive (High Impedance)
9th Bit Enable
PE
L or NC
Activate DQPx I/Os (x18/x3672 mode)
H
Deactivate DQPx I/Os (x16/x3272 mode)
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
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