參數(shù)資料
型號: GS881E18T-66I
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 512K x 18, 256K x 36 ByteSafe 8Mb Sync Burst SRAMs
中文描述: 512K X 18 CACHE SRAM, 18 ns, PQFP100
封裝: TQFP-100
文件頁數(shù): 4/34頁
文件大?。?/td> 487K
代理商: GS881E18T-66I
Rev: 1.10 9/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
4/34
2000, Giga Semconductor, Inc.
Preliminary
GS881E18/36T-11/11.5/100/80/66
TQFP Pin Descriptio
Pin Location
Symbol
Typ
e
I
Description
37, 36
A
0
, A
1
Address field LSBs and Address Counter preset Inputs
35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49, 50, 92
80
63, 62, 59, 58, 57, 56, 53, 52
68, 69, 72, 73, 74, 75, 78, 79
13, 12, 9, 8, 7, 6, 3, 2
18, 19, 22, 23, 24, 25, 28, 29
A
2
–A
17
I
Address Inputs
A
18
I
Address Inputs
DQ
A1
–DQ
A8
DQ
B1
–DQ
B8
DQ
C1
–DQ
C8
DQ
D1
–DQ
D8
DQ
A9
, DQ
B9
,
DQ
C9
, DQ
D9
DQ
A1
–DQ
A9
DQ
B1
–DQ
B9
I/O
Data Input and Output pins ( x36 Version)
51, 80, 1, 30
I/O
Data Input and Output pins
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
51, 52, 53, 56, 57
75, 78, 79,
1, 2, 3, 6, 7
25, 28, 29, 30
16
66
87
93, 94
95, 96
95, 96
89
88
98
97
86
83
84, 85
I/O
Data Input and Output pins
NC
No Connect
DP
QE
BW
B
A
, B
B
B
C
, B
D
NC
CK
GW
E
1
E
2
G
ADV
I
Parity Input; 1 = Even, 0 = Odd
Parity Error Out; Open Drain Output
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low
Byte Write Enable for DQ
C
, DQ
D
Data I/Os; active low ( x36 Version)
No Connect (x18 Version)
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
O
I
I
I
I
I
I
I
I
I
I
ADSP, ADSC
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GS881E18T-80 512K x 18, 256K x 36 ByteSafe 8Mb Sync Burst SRAMs
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