參數(shù)資料
型號(hào)： GS88136T-80
英文描述： x36 Fast Synchronous SRAM
中文描述： x36快速同步SRAM
文件頁(yè)數(shù)： 25/33頁(yè)
文件大小： 616K
代理商： GS88136T-80
Rev: 1.10 7/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
25/33
2000, Giga Semconductor, Inc.
Preliminary
GS88118/36T-11/11.5/100/80/66
only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table.
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when
the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices
in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the Instruc-
tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan
Register. Because the RAMclock is independent fromthe TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring con-
tents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm
the device, repeatable results cannot be expected. RAMinput signals must be stabilized for long enough to meet the TAPs input data cap-
ture set-up plus hold time (tTS plus tTH ). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O
ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the
TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update-
DR state with the SAMPLE / PRELOAD instruction loaded in the Instruction Register has the same effect as the Pause-DR command. This
functionality is not Standard 1149.1-compliant.
EXTEST
Select DR
Capture DR
0
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
1
Select IR
Capture IR
0
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
1
Test Logic Reset
Run Test Idle
0
1
0
1
1
0
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
Powered by ICminer.com Electronic-Library Service CopyRight 2003
相關(guān)PDF資料
PDF描述
GS88136T-80I x36 Fast Synchronous SRAM
GS9000
GS9000BCPJ SMPTE
GS9000BCTJ Converter
GS9000-CPJ SMPTE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS88136T-80I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM
GS8818/36T-11/11.5/100/80/66 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mb Sync Burst SRAMs
GS8819 功能描述:工業(yè)移動(dòng)感應(yīng)器和位置傳感器 RESISTIVE & OPTICAL RoHS:否 制造商:Honeywell 輸出類型:Analog - Current 電壓額定值:12 VDC to 30 VDC 線性:+/- 0.0011 % 溫度范圍:- 40 C to + 85 C 總電阻: 容差: 類型:Rotary Sensor
GS881E18 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
GS881E18AD-133 制造商:GSI 制造商全稱:GSI Technology 功能描述:512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*