Rev: 1.10 7/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
22/33
2000, Giga Semconductor, Inc.
Preliminary
GS88118/36T-11/11.5/100/80/66
Sleep Mode Timing Diagram
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in
a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in
transitions fromreads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to
manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised
to avoid excessive bus contention.
JTAG Port Operation
Overview
The JTAG Port on this RAMoperates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface standard
(commonly referred to as JTAG), but does not implement all of the functions required for 1149.1 compliance. Some functions have been modified
or elimnated because they can slow the RAM. Nevertheless, the RAMsupports 1149.1-1990 TAP (Test Access Port) Controller architecture, and
can be expected to function in a manner that does not conflict with the operation of Standard 1149.1 compliant devices. The JTAG Port
interfaces with conventional TTL / CMOS logic level signaling.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI,
and TMS are designed with internal pull-up circuits. To assure normal operation of the RAMwith the JTAG Port unused, TCK, TDI, and TMS may
be left floating or tied to either V
DD
or V
SS
. TDO should be left unconnected.
CK
ADSP
ADSC
tH
tKH tKL
tKC
tS
ZZ
tZZR
tZZH
tZZS
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Snooze
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