參數(shù)資料
型號: GS880Z18AT-133
廠商: Electronic Theatre Controls, Inc.
英文描述: 9Mb Pipelined and Flow Through Synchronous NBT SRAM
中文描述: 9MB的流水線和流量,通過同步唑的SRAM
文件頁數(shù): 4/25頁
文件大?。?/td> 753K
代理商: GS880Z18AT-133
Rev: 1.02 9/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
4/25
2001, Giga Semiconductor, Inc.
GS880Z18/36AT-250/225/200/166/150/133
100-Pin TQFP Pin Descriptions
Symbol
Type
A
0
, A
1
A
2
A
17
A
18
CK
B
A
B
B
B
C
B
D
W
E
1
E
2
E
3
G
ADV
CKE
NC
DQ
A1
DQ
A9
DQ
B1
DQ
B9
DQ
C1
DQ
C9
DQ
D1
DQ
D9
ZZ
FT
LBO
V
DD
V
SS
V
DDQ
Description
In
In
In
In
In
In
In
In
In
In
In
In
In
In
In
I/O
I/O
I/O
I/O
In
In
In
Burst Address Inputs; Preload the burst counter
Address Inputs
Address Input (x18 Version Only)
Clock Input Signal
Byte Write signal for data inputs DQ
A1
–DQ
A9
; active low
Byte Write signal for data inputs DQ
B1
–DQ
B9
; active low
Byte Write signal for data inputs DQ
C1
–DQ
C9
; active low
Byte Write signal for data inputs DQ
D1
–DQ
D9
; active low
Write Enable; active low
Chip Enable; active low
Chip Enable; Active High. For self decoded depth expansion
Chip Enable; Active Low. For self decoded depth expansion
Output Enable; active low
Advance/Load; Burst address counter control pin
Clock Input Buffer Enable; active low
No Connect
Byte A Data Input and Output pins
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
Power down control; active high
Pipeline/Flow Through Mode Control; active low
Linear Burst Order; active low
In
Core power supply
In
Ground
In
Output driver power supply
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