參數(shù)資料
型號： GS8662D18GE-333I
廠商： GSI TECHNOLOGY
元件分類： DRAM
英文描述： 72Mb SigmaQuad-II Burst of 4 SRAM
中文描述： 4M X 18 DDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
文件頁數(shù)： 22/29頁
文件大?。?/td> 896K
代理商： GS8662D18GE-333I
Preliminary
GS8662D08/09/18/36E-333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01a 2/2006
22/29
2005, GSI Technology
AC Electrical Characteristics
Parameter
Symbol
-333
-300
-250
-200
-167
Units
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Clock
K, K Clock Cycle Time
C, C Clock Cycle Time
t
KHKH
t
CHCH
3.0
3.5
3.3
4.2
4.0
6.3
5.0
7.88
6.0
8.4
ns
tKC Variable
t
KCVar
—
0.2
—
0.2
—
0.2
—
0.2
—
0.2
ns
5
K, K Clock High Pulse Width
C, C Clock High Pulse Width
t
KHKL
t
CHCL
1.2
—
1.32
—
1.6
—
2.0
—
2.4
—
ns
K, K Clock Low Pulse Width
C, C Clock Low Pulse Width
t
KLKH
t
CLCH
1.2
—
1.32
—
1.6
—
2.0
—
2.4
—
ns
K to K High
C to C High
t
KHKH
1.35
—
1.49
—
1.8
—
2.2
—
2.7
—
ns
K, K Clock High to C, C Clock High
t
KHCH
0
1.30
0
1.45
0
1.8
0
2.3
0
2.8
ns
DLL Lock Time
t
KCLock
1024
—
1024
—
1024
—
1024
—
1024
—
cycle
6
K Static to DLL reset
Output Times
t
KCReset
30
—
30
—
30
—
30
—
30
—
ns
K, K Clock High to Data Output Valid
C, C Clock High to Data Output Valid
t
KHQV
t
CHQV
—
0.45
—
0.45
—
0.45
—
0.45
—
0.5
ns
3
K, K Clock High to Data Output Hold
C, C Clock High to Data Output Hold
t
KHQX
t
CHQX
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.5
—
ns
3
K, K Clock High to Echo Clock Valid
C, C Clock High to Echo Clock Valid
t
KHCQV
t
CHCQV
—
0.45
—
0.45
—
0.45
—
0.45
—
0.5
ns
K, K Clock High to Echo Clock Hold
C, C Clock High to Echo Clock Hold
t
KHCQX
t
CHCQX
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.5
—
ns
CQ, CQ High Output Valid
t
CQHQV
—
0.25
—
0.27
—
0.30
—
0.35
—
0.40
ns
7
CQ, CQ High Output Hold
t
CQHQX
–0.25
—
–0.27
—
–0.30
—
–0.35
—
–0.40
—
ns
7
K Clock High to Data Output High-Z
C Clock High to Data Output High-Z
t
KHQZ
t
CHQZ
—
0.45
—
0.45
—
0.45
—
0.45
—
0.5
ns
3
K Clock High to Data Output Low-Z
C Clock High to Data Output Low-Z
t
KHQX1
t
CHQX1
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.5
—
ns
3
Setup Times
Address Input Setup Time
t
AVKH
0.4
—
0.4
—
0.5
—
0.6
—
0.7
—
ns
Control Input Setup Time
t
IVKH
0.4
—
0.4
—
0.5
—
0.6
—
0.7
—
ns
2
Data Input Setup Time
t
DVKH
0.28
—
0.3
—
0.35
—
0.4
—
0.5
—
ns
相關(guān)PDF資料
PDF描述
GS8662D36E-167 72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D36E-167I 72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D36E-200 72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D36E-200I 72Mb SigmaQuad-II Burst of 4 SRAM
GS8662D36E-250 72Mb SigmaQuad-II Burst of 4 SRAM
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