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參數(shù)資料
| 型號： | GS8644Z18E-V |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| 中文描述： | 72Mb流水線和流量，通過同步唑的SRAM |
| 文件頁數(shù)： | 20/30頁 |
| 文件大小： | 744K |
| 代理商： | GS8644Z18E-V |
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Instruction Register
ID Code Register
·
31 30 29
Boundary Scan Register
0
1
2
0
· · ·
1
2
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
1
·
1
0
·
·
·
·
·
·
·
·
·
Control Signals
·
Preliminary
GS8644Z18/36E-xxxV
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 6/2006
20/30
2003, GSI Technology
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Not Used
GSI Technology
JEDEC Vendor
ID Code
P
Bit #
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0 1 1 0 1 1 0 0 1
1
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