參數(shù)資料
型號: GS8642ZV72GC-250I
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 72Mb Pipelined and Flow Through Synchronous NBT SRAM
中文描述: 1M X 72 ZBT SRAM, 6.5 ns, PBGA209
封裝: 22 X 14 MM, 1 MM PITCH, LEAD FREE, BGA-209
文件頁數(shù): 23/32頁
文件大小: 805K
代理商: GS8642ZV72GC-250I
Instruction Register
ID Code Register
·
31 30 29
Boundary Scan Register
0
1
2
0
· · ·
1
2
0
Bypass Register
TDI
TDO
TMS
TCK
Test Access Port (TAP) Controller
1
·
1
0
·
·
·
·
·
·
·
·
·
Control Signals
·
Product Preview
GS8642ZV18(B)/GS8642ZV36(B)/GS8642ZV72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
23/32
2004, GSI Technology
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8642ZV72GC-300 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 72MBIT 1MX72 5.5NS/3NS 209FBGA - Trays
GS8642ZV72GC-300I 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM
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GS864418B 制造商:GSI 制造商全稱:GSI Technology 功能描述:4M x 18, 2M x 36, 1M x 72 72Mb S/DCD Sync Burst SRAMs
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