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參數(shù)資料
| 型號： | GS8642Z72GC-300 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | DRAM |
| 英文描述： | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| 中文描述： | 1M X 72 ZBT SRAM, 5.5 ns, PBGA209 |
| 封裝： | 22 X 14 MM, 1 MM PITCH, ROHS COMPLIANT, BGA-209 |
| 文件頁數(shù)： | 25/34頁 |
| 文件大?。?/td> | 872K |
| 代理商： | GS8642Z72GC-300 |
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ID Register Contents
Die
Revision
Code
Not Used
I/O
Configuration
GSI Technology
JEDEC Vendor
ID Code
P
Bit #
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
x72
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0 1 1 0 1 1 0 0 1
1
x36
X
X
X
X
0
0
0
X
1
0
0
1
0
0
0
0
1
0
0
0
0
0
0 1 1 0 1 1 0 0 1
1
x32
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0 1 1 0 1 1 0 0 1
1
x18
X
X
X
X
0
0
0
X
1
0
0
1
0
0
0
0
1
0
1
0
0
0
0 1 1 0 1 1 0 0 1
1
x16
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0 1 1 0 1 1 0 0 1
1
Product Preview
GS8642Z18(B)/GS8642Z36(B)/GS8642Z72(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 5/2005
25/34
2004, GSI Technology
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS8642Z72GC-300I | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8642Z18GB-200 | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8642Z18GB-200I | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8642Z18GB-250 | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8642Z18GB-250I | 72Mb Pipelined and Flow Through Synchronous NBT SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8642Z72GC-300I | 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 2.5V/3.3V 72MBIT 1MX72 5.5NS/3NS 209FBGA - Trays |
| GS8642Z72GC-300IV | 制造商:GSI Technology 功能描述:72MB S/DCD SYNCH BURST SRAM - Bulk |
| GS8642Z72GC-300V | 制造商:GSI Technology 功能描述:72MB S/DCD SYNCH BURST SRAM - Bulk |
| GS8642ZV18B | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8642ZV18B-167 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb Pipelined and Flow Through Synchronous NBT SRAM |
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