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參數(shù)資料
| 型號(hào)： | GS842Z18CB-250T |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 256K X 18 ZBT SRAM, 5.5 ns, PBGA119 |
| 封裝： | FPBGA-119 |
| 文件頁數(shù)： | 25/29頁 |
| 文件大?。?/td> | 248K |
| 代理商： | GS842Z18CB-250T |
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GS842Z18CB/GS842Z36CB
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01 8/2011
5/29
2011, GSI Technology
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipelined Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three
chip enables (E1, E2, and E3) are active, the write enable input signal W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins.
Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The
Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write cycle
with no Byte Write inputs active is a no-op cycle. The Pipelined NBT SRAM provides double late write functionality, matching the
write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising
edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the
third rising edge of clock.
Flow through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use
of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new
address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way as well, but differ in that the write pipeline is one cycle shorter as well, preserving
the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a
double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode,
address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising
edge of clock.
Function
W
BA
BB
BC
BD
Read
H
X
XXX
Write Byte “a”
L
H
Write Byte “b”
L
H
L
H
Write Byte “c”
L
H
L
H
Write Byte “d”
L
H
L
Write all Bytes
L
LLLL
Write Abort/NOP
L
H
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| GS842Z18CGB-100 | 制造商:GSI Technology 功能描述:119 BGA - Bulk |
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| GS842Z36AB-100I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:4Mb Pipelined and Flow Through Synchronous NBT SRAMs |
| GS842Z36AB-150 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:4Mb Pipelined and Flow Through Synchronous NBT SRAMs |
| GS842Z36AB-150I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:4Mb Pipelined and Flow Through Synchronous NBT SRAMs |
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