參數(shù)資料
型號(hào)： GS8342TT06BGD-500T
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 4M X 8 DDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
文件頁(yè)數(shù)： 10/30頁(yè)
文件大?。?/td> 267K
代理商： GS8342TT06BGD-500T
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 5/2011
18/30
2011, GSI Technology
Preliminary
GS8342TT06/11/20/38BD-550/500/450/400/350
AC Electrical Characteristics
Parameter
Symbol
-550
-500
-450
-400
-350
Units
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Clock
K, K Clock Cycle Time
tKHKH
1.81
8.4
2.0
8.4
2.2
8.4
2.5
8.4
2.86
8.4
ns
tK Variable
tKVar
—
0.15
—
0.15
—
0.15
—
0.2
—
0.2
ns
4
K, K Clock High Pulse Width
tKHKL
0.4
—
0.4
—
0.4
—
0.4
—
0.4
—
cycle
K, K Clock Low Pulse Width
tKLKH
0.4
—
0.4
—
0.4
—
0.4
—
0.4
—
cycle
K to K High
tKHKH
0.77
—
0.85
—
0.94
—
1.06
—
1.13
—
ns
K to K High
tKHKH
0.77
—
0.85
—
0.94
—
1.06
—
1.13
—
ns
DLL Lock Time
tKLock
2048
—
2048
—
2048
—
2048
—
2048
—
cycle
5
K Static to DLL reset
tKReset
30
—
30
—
30
—
30
—
30
—
ns
Output Times
K, K Clock High to Data Output Valid
tKHQV
—
0.45
—
0.45
—
0.45
—
0.45
—
0.45
ns
K, K Clock High to Data Output Hold
tKHQX
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.45
—
ns
K, K Clock High to Echo Clock Valid
tKHCQV
—
0.45
—
0.45
—
0.45
—
0.45
—
0.45
ns
K, K Clock High to Echo Clock Hold
tKHCQX
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.45
—
ns
CQ, CQ High Output Valid
tCQHQV
—
0.15
—
0.15
—
0.15
—
0.2
—
0.23
ns
CQ, CQ High Output Hold
tCQHQX
–0.15
—
–0.15
—
–0.15
—
–0.2
—
–0.23
—
ns
CQ, CQ High to QLVD
tQVLD
–0.15
0.15
–0.15
0.15
–0.15
0.15
–0.2
0.2
–0.23
0.23
ns
CQ Phase Distortion
tCQHCQH
0.655
—
0.75
—
0.85
—
1.0
—
1.0
—
ns
K Clock High to Data Output High-Z
tKHQZ
—
0.45
—
0.45
—
0.45
—
0.45
—
0.45
ns
K Clock High to Data Output Low-Z
tKHQX1
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.45
—
ns
Setup Times
Address Input Setup Time
tAVKH
0.25
—
0.25
—
0.275
—
0.4
—
0.4
—
ns
1
Control Input Setup Time
(R/W)
tIVKH
0.25
—
0.25
—
0.275
—
0.4
—
0.4
—
ns
2
Control Input Setup Time
(BWX)
tIVKH
0.20
—
0.20
—
0.22
—
0.28
—
0.28
—
ns
3
Data Input Setup Time
tDVKH
0.20
—
0.20
—
0.22
—
0.28
—
0.28
—
ns
Hold Times
Address Input Hold Time
tKHAX
0.25
—
0.25
—
0.275
—
0.4
—
0.4
—
ns
1
Control Input Hold Time
(R/W)
tKHIX
0.25
—
0.25
—
0.275
—
0.4
—
0.4
—
ns
2
Control Input Hold Time
(BWX)
tKHIX
0.20
—
0.20
—
0.22
—
0.28
—
0.28
—
ns
3
Data Input Hold Time
tKHDX
0.20
—
0.20
—
0.22
—
0.28
—
0.28
—
ns
Notes:
1. All Address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control signals are R/W, LD.
3. Control signals are BW0, BW1 and (BW2, BW3 for x36).
4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
5. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable.
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