參數(shù)資料
型號(hào)： GS8342S36AE-200S
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 1M X 36 DDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, 1 MM PITCH, MO-216CAB-1, FPBGA-165
文件頁(yè)數(shù)： 14/37頁(yè)
文件大小： 1576K
代理商： GS8342S36AE-200S
Preliminary
GS8342S08/09/18/36AE-333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 6/2006
21/37
2006, GSI Technology
Hold Times
Address Input Hold Time
tKHAX
0.4
—
0.4
—
0.5
—
0.6
—
0.7
—
ns
Control Input Hold Time
tKHIX
0.4
—
0.4
—
0.5
—
0.6
—
0.7
—
ns
Data Input Hold Time
tKHDX
0.28
—
0.3
—
0.35
—
0.4
—
0.5
—
ns
Notes:
1. All Address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control singles are R, W, BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36).
3. If C, C are tied high, K, K become the references for C, C timing parameters
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus conten-
tion because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX
parameter (worst case at 70°C, 1.7 V). It is not possible for two SRAMs on the same board to be at such different voltages and tempera-
tures.
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable.
7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet
parameters reflect tester guard bands and test setup variations.
AC Electrical Characteristics (Continued)
Parameter
Symbol
-333
-300
-250
-200
-167
Units
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
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