參數(shù)資料
型號(hào)： GS8342QT10BGD-300T
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 4M X 9 QDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, 1 MM PITCH, FPBGA-165
文件頁(yè)數(shù)： 30/30頁(yè)
文件大?。?/td> 306K
代理商： GS8342QT10BGD-300T
Preliminary
GS8342QT07/10/19/37BD-357/333/300/250/200
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 5/2011
9/30
2011, GSI Technology
Separate I/O SigmaQuad-II B2 SRAM Read Truth Table
AR
Output Next State
Q
K
(tn)
K
(tn)
K
(tn)
K
(tn+2)
K
(tn+2)
X
1
Deselect
Hi-Z
V
0
Read
Q0
Q1
Notes:
1. X = Don’t Care, 1 = High, 0 = Low, V = Valid.
2. R is evaluated on the rising edge of K.
3. Q0 and Q1 are the first and second data output transfers in a read.
Separate I/O SigmaQuad-II B2 SRAM Write Truth Table
AW
BWn/NWn BWn/NWn
Input Next State
D
K
(tn + )
K
(tn)
K
(tn)
K
(tn + )
K
K
(tn), (tn + )
K
(tn)
K
(tn + )
V
0
Write Byte Dx0, Write Byte Dx1
D0
D1
V
0
1
Write Byte Dx0, Write Abort Byte Dx1
D0
X
V
0
1
0
Write Abort Byte Dx0, Write Byte Dx1
X
D1
X
0
1
Write Abort Byte Dx0, Write Abort Byte Dx1
X
X1X
X
Deselect
X
Notes:
1. X = Don’t Care, H = High, L = Low, V = Valid.
2. W is evaluated on the rising edge of K.
3. D0 and D1 are the first and second data input transfers in a write.
4. BWn represents any of the Byte Write Enable inputs (BW0, BW1, etc.). NWn represents any of the Nybble Write Enable inputs (NW0,
NW1).
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