參數(shù)資料
型號(hào)： GS8342D37BD-300I
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 1M X 36 QDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, 1 MM PITCH, FPBGA-165
文件頁(yè)數(shù)： 30/30頁(yè)
文件大小： 962K
代理商： GS8342D37BD-300I
Preliminary
GS8342D07/10/19/37BD-450/400/350/333/300
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 4/2011
9/30
2011, GSI Technology
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II+ SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 175
Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps.
Input Termination Impedance Control
These SigmaQuad-II+ SRAMs are supplied with programmable input termination on Data (D), Byte Write (BW), and Clock (K/K)
input receivers. Input termination can be enabled or disabled via the ODT pin (6R). When the ODT pin is tied Low (or left
floating —the pin has a small pull-down resistor), input termination is disabled. When the ODT pin is tied High, input termination
is enabled. Termination impedance is programmed via the same RQ resistor (connected between the ZQ pin and VSS) used to
program output driver impedance, and is nominally RQ*0.6 Thevenin-equivalent when RQ is between 175
Ω and 250Ω. Periodic
readjustment of the termination impedance occurs to compensate for drifts in supply voltage and temperature, in the same manner
as for driver impedance (see above).
Note:
When ODT = 1, Data (D), Byte Write (BW), and Clock (K, K) input termination is always enabled. Consequently, D, BW, K, K
inputs should always be driven High or Low; they should never be tri-stated (i.e., in a High-Z state). If the inputs are tri-stated, the
input termination will pull the signal to VDDQ/2 (i.e., to the switch point of the diff-amp receiver), which could cause the receiver
to enter a meta-stable state and prevent the SRAM from operating within specification.
Separate I/O SigmaQuad II+ B4 SRAM Truth Table
Previous
Operation
A
R
W
Current
Operation
D
Q
K
↑
(tn-1)
K
↑
(tn)
K
↑
(tn)
K
↑
(tn)
K
↑
(tn)
K
↑
(tn+1)
K
↑
(tn+1)
K
↑
(tn+2)
K
↑
(tn+2)
K
↑
(tn+2)
K
↑
(tn+2)
K
↑
(tn+3)
K
↑
(tn+3)
Deselect
X
1
Deselect
X
—
Hi-Z
—
Write
X
1
X
Deselect
D2
D3
—
Hi-Z
—
Read
X
1
Deselect
X
—
Q2
Q3
—
Deselect
V
1
0
Write
D0
D1
D2
D3
Hi-Z
—
Deselect
V
0
X
Read
X
—
Q0
Q1
Q2
Q3
Read
V
X
0
Write
D0
D1
D2
D3
Q2
Q3
—
Write
V
0
X
Read
D2
D3
—
Q0
Q1
Q2
Q3
Notes:
1. “1” = input “high”; “0” = input “l(fā)ow”; “V” = input “valid”; “X” = input “don’t care”
2. “—” indicates that the input requirement or output state is determined by the next operation.
3. Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations.
4. D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations.
5. Users should not clock in metastable addresses.
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