參數(shù)資料
型號: GS82032AT-4I
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 64K X 32 CACHE SRAM, 10 ns, PQFP100
封裝: TQFP-100
文件頁數(shù): 9/22頁
文件大?。?/td> 750K
代理商: GS82032AT-4I
GS82032AT-180/166/150/133/100/66/4/5/6
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.13 1/2009
17/22
2000, GSI Technology
Sleep Mode Timing
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on
dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address
boundary crossings), but greater care must be exercised to avoid excessive bus contention.
tZZR
tZZH
tZZS
Hold
Setup
tKL
tKH
tKC
CK
ADSP
ADSC
ZZ
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