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參數(shù)資料
| 型號(hào)： | GS820322T-138 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | 64K x 32 2M Synchronous Burst SRAM |
| 中文描述： | 64K的× 32 200萬(wàn)同步突發(fā)靜態(tài)存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 8/23頁(yè) |
| 文件大?。?/td> | 760K |
| 代理商： | GS820322T-138 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)當(dāng)前第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)
Rev: 1.04 2/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
8/23
2000, Giga Semiconductor, Inc.
Preliminary
GS82032T/Q-150/138/133/117/100/66
Simplified State Diagram with G
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
X
W
R
R
W
R
X
X
X
CR
R
CW
CR
CR
W
CW
W
CW
Notes:
1.
2.
The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a deselect cycle. Dummy read cycles increment the address counter just like normal read cycles.
Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
3.
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| GS82032Q-117 | 64K x 32 2M Synchronous Burst SRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| GS82032A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2M Synchronous Burst SRAM |
| GS82032AGQ-133 | 制造商:GSI Technology 功能描述:2MB (64K X 32) SYNCH BURST SCD - Trays |
| GS82032AGQ-133I | 制造商:GSI Technology 功能描述:2MB (64K X 32) SYNCH BURST SCD - Trays |
| GS82032AGQ-150I | 制造商:GSI Technology 功能描述:2MB (64K X 32) SYNCH BURST SCD - Trays |
| GS82032AGQ-166 | 制造商:GSI Technology 功能描述:2MB (64K X 32) SYNCH BURST SCD - Trays |
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