參數(shù)資料
型號(hào)： GS8182S18BD-250I
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 1M X 18 DDR SRAM, 0.45 ns, PBGA165
封裝： 13 X 15 MM, 1 MM PITCH, FPBGA-165
文件頁(yè)數(shù)： 4/37頁(yè)
文件大?。?/td> 564K
代理商： GS8182S18BD-250I
GS8182S08/09/18/36BD-400/375/333/300/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03b 6/2010
12/37
2007, GSI Technology
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaSIO DDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected
to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching
with a vendor-specified tolerance is between 175
Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as
the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for
drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts
again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level.
Separate I/O Burst of 2 Sigma SIO-II SRAM Truth Table
A
LD
R/W
Current
Operation
D
Q
K
↑
(tn)
K
↑
(tn)
K
↑
(tn)
K
↑
(tn)
K
↑
(tn+1)
K
↑
(tn+1)
K
↑
(tn+1)
K
↑
(tn+1)
X
1
X
Deselect
X
—
Hi-Z
—
V
0
1
Read
X
—
Q0
Q1
V
0
Write
D0
D1
Hi-Z
—
Notes:
1. “1” = input “high”; “0” = input “l(fā)ow”; “V” = input “valid”; “X” = input “don’t care”
2. “—” indicates that the input requirement or output state is determined by the next operation.
3. Q0 and Q1 indicate the first and second pieces of output data transferred during Read operations.
4. D0 and D1 indicate the first and second pieces of input data transferred during Write operations.
5. Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when pre-
ceded by a Read command.
6. CQ is never tristated.
7. Users should not clock in metastable addresses.
x18 Byte Write Clock Truth Table
BW
Current Operation
D
K
↑
(tn+1)
K
↑
(tn+2)
K
↑
(tn)
K
↑
(tn+1)
K
↑
(tn+2)
T
Write
Dx stored if BWn = 0 in both data transfers
D1
D2
T
F
Write
Dx stored if BWn = 0 in 1st data transfer only
D1
X
F
T
Write
Dx stored if BWn = 0 in 2nd data transfer only
X
D2
F
Write Abort
No Dx stored in either data transfer
X
Notes:
1. “1” = input “high”; “0” = input “l(fā)ow”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
相關(guān)PDF資料
PDF描述
GS8182S18BD-300I 1M X 18 DDR SRAM, 0.45 ns, PBGA165
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8182S18D-250 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 18MBIT 1MX18 0.45NS 165FBGA - Trays
GS8182S18D-250I 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 18MBIT 1MX18 0.45NS 165FPBGA - Trays
GS8182S36BD-167 制造商:GSI Technology 功能描述:512K X 36 (18 MEG) BURST OF 2 - Trays
GS8182S36BD-167I 制造商:GSI Technology 功能描述:512K X 36 (18 MEG) BURST OF 2 - Trays
GS8182S36BD-200 制造商:GSI Technology 功能描述:512K X 36 (18 MEG) BURST OF 2 - Trays
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