參數(shù)資料
型號(hào)： GS8170DW72AGC-350
廠商： GSI TECHNOLOGY
元件分類： DRAM
英文描述： 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
中文描述： 256K X 72 STANDARD SRAM, 1.6 ns, PBGA209
封裝： 14 X 22 MM, 1 MM PITCH, LEAD FREE, BGA-209
文件頁(yè)數(shù)： 13/32頁(yè)
文件大?。?/td> 766K
代理商： GS8170DW72AGC-350
GS8170DW36/72AC-350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2005
13/32
2003, GSI Technology
Double Late Write, Pipelined Read Truth Table
CK
E1
(t
n
)
E
(t
n
)
ADV
(t
n
)
W
(t
n
)
B
(t
n
)
Previous
Operation
Current Operation
DQ/CQ
(t
n
)
DQ/CQ
(t
n+1
)
DQ/CQ
(t
n+2
)
0
→
1
X
F
0
X
X
X
Bank Deselect
***/***
Hi-Z/Hi-Z
---
0
→
1
X
X
1
X
X
Bank Deselect
Bank Deselect (Continue)
Hi-Z/Hi-Z
Hi-Z/Hi-Z
---
0
→
1
1
T
0
X
X
X
Deselect
***/***
Hi-Z/CQ
---
0
→
1
X
X
1
X
X
Deselect
Deselect (Continue)
Hi-Z/CQ
Hi-Z/CQ
---
0
→
1
0
T
0
0
T
X
Write
Loads new address
Stores DQx if Bx = 0
***/***
***/***
D1/CQ
0
→
1
0
T
0
0
F
X
Write (Abort)
Loads new address
No data stored
***/***
***/***
Hi-Z/CQ
0
→
1
X
X
1
X
T
Write
Write Continue
Increments address by 1
Stores DQx if Bx = 0
***/***
Dn-1/CQ
Dn/CQ
0
→
1
X
X
1
X
F
Write
Write Continue (Abort)
Increments address by 1
No data stored
***/***
Dn-1/CQ
Hi-Z/CQ
0
→
1
0
T
0
1
X
X
Read
Loads new address
***/***
Q1/CQ
---
0
→
1
X
X
1
X
X
Read
Read Continue
Increments address by 1
Qn-1/CQ
Qn/CQ
---
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
If E2 = EP2 and E3 = EP3, then E = “T” else E = “F”.
If one or more Bx = 0, then B = “T” else B = “F”.
“1” = input “high”; “0” = input “l(fā)ow”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
“***” indicates that the DQ input requirement / output state and CQ output state are determined by the previous operation.
“---” indicates that the DQ input requirement / output state and CQ output state are determined by the next operation.
DQs are tristated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled.
CQs are tristated in response to Bank Deselect commands only, one full cycle after the command is sampled.
Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four (4) distinct pieces
of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the initial exter-
nal (base) address.
相關(guān)PDF資料
PDF描述
GS8170DW72AGC-350I 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
GS8170DW36AC-250 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
GS8170DW36AC-250I 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
GS8170DW36AC-300 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
GS8170DW36AC-300I 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8170DW72AGC-350I 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 1.7NS 209FBGA - Trays
GS8170LW36AC-300I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.8NS 209FBGA - Trays
GS8170LW36AGC-250 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays
GS8170LW36AGC-250I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays
GS8170LW36AGC-350 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209FBGA - Trays
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