參數(shù)資料
型號(hào)： GS8170DW36AC-350
廠商： GSI TECHNOLOGY
元件分類： DRAM
英文描述： 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
中文描述： 512K X 36 STANDARD SRAM, 1.6 ns, PBGA209
封裝： 14 X 22 MM, 1 MM PITCH, BGA-209
文件頁(yè)數(shù)： 4/32頁(yè)
文件大?。?/td> 766K
代理商： GS8170DW36AC-350
GS8170DW36/72AC-350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2005
4/32
2003, GSI Technology
Operation Control
All address, data and control inputs (with the exception of EP2, EP3, ZQ, and the mode pins, L6, M6, and J6) are synchronized to
rising clock edges. Data in is captured on both rising and falling edges of CK. Read and write operations must be initiated with the
Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of
the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device.
It should be noted
that ONLY deactivation of the RAM via E2 and/or E3 deactivates the Echo Clocks, CQ1–CQ2.
Pin Description Table
Symbol
Description
Type
Comments
A
Address
Input
—
ADV
Advance
Input
Active High
Bx
Byte Write Enable
Input
Active Low
W
Write Enable
Input
Active Low
E1
Chip Enable
Input
Active Low
E2 & E3
Chip Enable
Input
Programmable Active High or Low
EP2 & EP3
Chip Enable Program Pin
Mode Input
To be tied directly to V
DD
, V
DDQ
or V
SS
CK
Clock
Input
Active High
CQ, CQ
Echo Clock
Output
Three State - Deselect via E2 or E3 False
DQ
Data I/O
Input/Output
Three State
MCH
Must Connect High
Input
Active High
To be tied directly to V
DD
or V
DDQ
MCL
Must Connect Low
Input
Active Low
To be tied directly to V
SS
ZQ
Output Impedance Control
Mode Input
Low = Low Impedance [High Drive]
High = High Impedance [Low Drive]
To be tied directly to V
DDQ
or V
SS
TCK
Test Clock
Input
Active High
TDI
Test Data In
Input
—
TDO
Test Data Out
Output
—
TMS
Test Mode Select
Input
—
NC
No Connect
—
Not connected to die or any other pin
V
DD
Core Power Supply
Input
1.8 V Nominal
V
DDQ
Output Driver Power Supply
Input
1.8 V Nominal
V
SS
Ground
Input
—
相關(guān)PDF資料
PDF描述
GS8170DW36AC-350I 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
GS8170DW36AGC-250 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
GS8170DW36AGC-250I 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
GS8170DW36AGC-300 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
GS8170DW36AGC-300I 18Mb ヒ1x1Dp CMOS I/O Double Late Write SigmaRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8170DW36AC-350I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.7NS 209FBGA - Trays
GS8170DW36AGC-250 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays
GS8170DW36AGC-250I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 2.1NS 209FBGA - Trays
GS8170DW36AGC-300 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.8NS 209FBGA - Trays
GS8170DW36AGC-300I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V 18MBIT 512KX36 1.8NS 209FBGA - Trays
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