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參數(shù)資料
| 型號： | GMZAN3T |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | XGA ALALOG INTERFACE LCD MONITOR CONTROLLER |
| 中文描述： | ALALOG的XGA液晶顯示器接口控制器 |
| 文件頁數(shù)： | 30/53頁 |
| 文件大?。?/td> | 556K |
| 代理商： | GMZAN3T |
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gmZAN3 Preliminary Data Sheet
C0523-DAT-01G
36
July 2003
Ge nes i s Microc hip Confid e n tia l
http:// w ww . g enesis-mic r ochip.com
Free Run Mode: No synchronization. This mode is used when there is no valid input timing (i.e. to
display OSD messages or a splash screen) or for testing purposes. In free-run mode, the display
timing is determined only by the values programmed into the display window and timing registers.
4.8.2 Programming the Display Timing
Display timing signals provide timing information so the Display Port can be connected to an external
display device. Based on values programmed in registers, the Display Output Port produces the
horizontal sync (DHS), vertical sync (DVS), and data enable (DEN) control signals, which are then
encoded into the LVDS data stream by the on-chip LVDS transmitter. The figure below provides the
registers that define the output display timing.
Horizontal values are programmed in single pixel increments relative to the leading edge of the horizontal
sync signal. Vertical values are programmed in line increments relative to the leading edge of the vertical
sync signal.
Display Active Window
Display Background Window
Vertical Blanking (Back Porch)
VSYNC Region
H
o
rizontal
Bl
anki
ng
(
B
ack
Por
ch)
H
SYN
C
r
egi
on
DV_VS_END
DEN **
DHS
DV_BKGND_START
DV_ACTIVE_START
DV_ACTIVE_LENGTH
DVS
DV_BKGND_END
DV
_
T
OTA
L
DH_HS_END
DH_BKGND_START
DH_BKGND_END
DH_TOTAL
DH_ACTIVE_START
DH_ACTIVE_WIDTH
Vertical Blanking (Front Porch)
H
o
rizontal
Bl
anki
ng
(
F
ront
Por
ch)
** DEN is not asserted during vertical blanking
Figure 21.
Display Windows and Timing
The double-wide (TTL only) output only supports an even number of horizontal pixels.
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