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參數(shù)資料
| 型號： | GMZAN3L |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | XGA ALALOG INTERFACE LCD MONITOR CONTROLLER |
| 中文描述： | ALALOG的XGA液晶顯示器接口控制器 |
| 文件頁數(shù)： | 44/53頁 |
| 文件大?。?/td> | 556K |
| 代理商： | GMZAN3L |
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gmZAN3 Preliminary Data Sheet
C0523-DAT-01G
49
July 2003
Ge nes i s Microc hip Confid e n tia l
http:// w ww . g enesis-mic r ochip.com
5.2 Preliminary AC Characteristics
The following targeted specifications have been derived by simulation.
All timing is measured to a 1.5V logic-switching threshold. The minimum and maximum operating
conditions used were: TDIE = 0 to 125° C, Vdd = 1.71 to 1.89V, Process = best to worst, CL = 16pF for all outputs.
Table 24.
Maximum Speed of Operation
Clock Domain
Max Speed of Operation
Main Input Clock (TCLK)
24MHz (14.3MHz recommended)
ADC Clock (ACLK)
100MHz
HCLK Host Interface Clock (6-wire protocol)
5MHz
Reference Clock (RCLK)
240MHz (220MHz recommended)
Display Clock (DCLK)
90MHz
Table 25.
Display Timing and DCLK Adjustments
DP_TIMING ->
Tap 0 (default)
Tap 1
Tap 2
Tap 3
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Propagation delay from DCLK to DA*/DB*
1.0
4.5
0.5
3.5
-0.5
2.5
-1.5
1.5
Propagation delay from DCLK to DHS
1.0
4.5
0.5
3.5
-0.5
2.5
-1.5
1.5
Propagation delay from DCLK to DVS
0.5
4.5
0.0
3.5
-1.0
2.5
-2.0
1.5
Propagation delay from DCLK to DEN
1.0
4.5
0.5
3.5
-0.5
2.5
-1.5
1.5
Note: DCLK Clock Adjustments are the amount of additional delay that can be inserted in the DCLK path, in order to reduce the
propagation delay between DCLK and its related signals.
Table 26.
2-Wire Host Interface Port Timing
Parameter
Symbol
MIN
TYP
MAX
Units
SCL HIGH time
TSHI
1.25
us
SCL LOW time
TSLO
1.25
us
SDA to SCL Setup
TSDIS
30
ns
SDA from SCL Hold
TSDIH
20
ns
Propagation delay from SCL to SDA
TSDO3
10
150
ns
Note: The above table assumes OCM_CLK = R_CLK / 2 = 100 MHz (default) (ie 10ns / clock)
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