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| 型號： | GM5120-H |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | XGA/SXGA LCD Controller |
| 中文描述： | 的XGA / SXGA LCD控制器 |
| 文件頁數(shù)： | 23/51頁 |
| 文件大?。?/td> | 1379K |
| 代理商： | GM5120-H |
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***
Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
June 2002
16
C5110-DAT-01C
S C L K
S E N S E _ A C L K
D V I _ C L K
I P _ C L K
D C L K
I P _ C L K
D P _ C L K
S C L K
A C L K
O C M _ C L K
R C L K / 2
T C L K
I F M _ C L K
T C L K
R C L K / 4
Figure 9.
On-chip Clock Domains
4
4
.
.
2
2
H
H
a
a
r
r
d
d
w
w
a
a
r
r
e
e
R
R
e
e
s
s
e
e
t
t
Hardware Reset is performed by holding the RESETn pin low for a minimum of 1
μ
s. A
TCLK input (see Clock Options above) must be applied during and after the reset. When the
reset period is complete and RESETn is de-asserted, the power-up sequence is as follows:
1. Reset all registers of all types to their default state (this is 00h unless otherwise specified
in the gm5110/20 Register Listing).
2. Force each clock domain into reset. Reset will remain asserted for 64 local clock domain
cycles following the de-assertion of RESETn.
3. Operate the OCM_CLK domain at the TCLK frequency.
4. Preset the RCLK PLL to output ~200MHz clock (assumes 14.3MHz TCLK crystal
frequency).
5. Wait for RCLK PLL to Lock. Then, switch the OCM_CLK domain to operate from the
bootstrap selected clock.
6. If a pull-up resistor is installed on ROM_ADDR9 pin (see Table 18), then the OCM
becomes active as soon as OCM_CLK is stable. Otherwise, the OCM remains in reset
until OCM_CONTROL register (0x22) bit 1 is enabled.
4
4
.
.
3
3
A
A
n
n
a
a
l
l
o
o
g
g
t
t
o
o
D
D
i
i
g
g
i
i
t
t
a
a
l
l
C
C
o
o
n
n
v
v
e
e
r
r
t
t
e
e
r
r
The gm5110/20 chip has three ADC’s (analog-to-digital converters), one for each color (red,
green, and blue).
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