參數(shù)資料
型號(hào)： GM5115
廠商： Electronic Theatre Controls, Inc.
英文描述： ONPANEL LCD PANEL CONTROLLER
中文描述： ONPANEL液晶顯示器控制器
文件頁(yè)數(shù)： 36/58頁(yè)
文件大?。?/td> 1505K
代理商： GM5115
***
Genesis Microchip Confidential ***
gm5115/25 Preliminary Data Sheet
June 2002
27
C5115-DAT-01H
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The gm5115/25 has the capability to completely bypass internal processing. In this case,
captured input signals and data are passed, with a small latency, straight through to the display
output. The gm5115/25 is also able to bypass the zoom filter and the gamma LUT.
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The gm5115/25 provides an 8 to 10-bit look-up table (LUT) for each input color channel
intended for Gamma correction and to compensate for a non-linear response of the LCD panel.
A 10-bit output results in an improved color depth control. The 10-bit output is then dithered
down to 8 bits (or 6 bits) per channel at the display (see section 4.11.3 below). The LUT is user-
programmable to provide an arbitrary transfer function. Gamma correction occurs after the zoom
/ shrink scaling block. If bypassed, the LUT does not require programming.
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The Display Output Port provides data and control signals that permit the gm5115/25 to connect
to a variety of flat panel or CRT devices. The output interface is configurable for 18 or 24-bit
RGB pixels, either single- or double-pixel wide. All display data and timing signals are
synchronous with the DCLK output clock.
4.11.1 Display Synchronization
Refer to section 4.1 for information regarding internal clock synthesis.
The gm5115/25 supports the following display synchronization modes:
Frame Sync Mode:
The display frame rate is synchronized to the input frame or field
rate. This mode is used for standard operation.
Free Run Mode:
No synchronization. This mode is used when there is no valid input
timing (i.e. to display OSD messages or a splash screen) or for testing purposes. In free-
run mode, the display timing is determined only by the values programmed into the
display window and timing registers.
4.11.2 Programming the Display Timing
Display timing signals provide timing information so the Display Port can be connected to an
external display device. Based on values programmed in registers, the Display Output Port
produces the horizontal sync (DHS), vertical sync (DVS), and data enable (DEN) control signals.
The figure below provides the registers that define the output display timing.
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