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參數(shù)資料
| 型號： | GCIXF1002ED |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 7/128頁 |
| 文件大?。?/td> | 1262K |
| 代理商： | GCIXF1002ED |
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Datasheet
vii
Intel
IXF1002 Dual Port Gigabit Ethernet Controller
Figures
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Block Diagram......................................................................................................9
Full-64 IX Bus Mode............................................................................................60
Narrow IX Bus Mode...........................................................................................60
Split IX Bus Mode................................................................................................60
Little Endian, Full-64 Bus Mode (BEND=0, FIFMD=01)......................................61
Little Endian, Split Bus Mode (BEND=0, FIFMD=10)..........................................61
Little Endian, Narrow Bus Mode (BEND=0, FIFMD=00).....................................61
Big Endian, Full-64 Bus Mode (BEND=1, FIFMD=01)........................................61
Big Endian, Split Bus Mode (BEND=0, FIFMD=10)............................................61
Big Endian, Narrow Bus Mode (BEND=1, FIFMD=00)........................................61
VLAN Tagged MAC Frame Format.....................................................................63
VLAN Tag Append ..............................................................................................65
VLAN Tag Strip ...................................................................................................65
VLAN Tag Replace..............................................................................................66
Transmit Flow Diagram .......................................................................................67
Receive Flow Diagram ........................................................................................72
MAC Frame Format.............................................................................................79
Transmit Start-of-Packet Timing..........................................................................87
Transmit End-of-Packet Timing...........................................................................88
Transmit Packet Timing in Split Mode.................................................................88
Transmit packet with VLAN Tag Append Timing.................................................89
Transmit packet with VLAN Tag Strip Timing......................................................90
Transmit packet with VLAN Tag Replace Timing................................................91
VLAN Tag Append in Two txsel_l Bursts Timing.................................................92
VLAN Tag Replace in Two txsel_l Bursts Timing................................................93
Transmit FIFO Control Timing.............................................................................93
Transmit txrdy Timing..........................................................................................94
Receive Start-of-Packet Timing...........................................................................94
Receive End-of-Packet Timing............................................................................95
Receive Packet Timing in Split Mode..................................................................96
Receive rxfail Timing...........................................................................................97
Receive rxabt Timing...........................................................................................98
Receive rxkep Timing..........................................................................................99
Receive Header Replay Timing.........................................................................100
Receive FIFO Control Timing............................................................................100
Receive rxrdy Timing.........................................................................................101
Consecutive Transmit-Transmit Timing.............................................................101
Consecutive Transmit-Receive Timing..............................................................102
Consecutive Receive-Transmit Timing..............................................................102
Consecutive Receive-Receive Timing...............................................................103
Packet Transmission Timing.............................................................................103
Packet Reception Timing ..................................................................................104
False Carrier Timing..........................................................................................104
IX Bus Clock Timing Diagram ...........................................................................106
IX Bus Signals Timing Diagram.........................................................................108
CPU Port Read Timing Diagram.......................................................................109
CPU Port Write Timing Diagram .......................................................................110
GMII Clock Timing Diagram ..............................................................................111
GPCS Transmit Clock Timing Diagram.............................................................111
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| GCIXF1024EC.A3-884561 | 功能描述:IC ETHERNET MAC 24PORT 672-BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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