
MOTOROLA
Chapter 10. Power Management
10-7
Example Code Sequence for Entering Processor Sleep Mode
ori r0, r0, 0x4000 # enable the Dcache DCE
ori r0, r0, 0x0800 # invalidate Icache ICFI
ori r0, r0, 0x0400 # invalidate Dcache DCFI
mtspr hid0, r0
isync
#******************************************************************
# then when the processor is in a loop, force an SMI interrupt
#******************************************************************
.orig 0x00001400
# System Management Interrupt
# force big-endian mode
stw r0,0x05f8,r0
stw r0,0x05fc,r0
mfmsr r0
ori r0,r0,r0
ori r0,r0,0x0001
ori r0,r0,r0
xori r0,r0,0x0001
ori r0,r0,r0
mtmsr r0
ori r0,r0,r0
isync
ori r0,r0,r0
# need nop every second inst.
# force big-endian LE bit
# force big-endian LE bit
# save off additional registers to be corrupted
stw r20,0x05f4,r0
mfspr r21, srr0
stw r21,0x05f0,r0
mfspr r22, srr1
stw r22,0x05ec,r0
stw r23,0x05e8,r0
mfcr r23
stw r23,0x05e4,r0
xor r0,r0,r0
# put srr0 in r21
# put r21 in 0x05f0
# put srr1 in r22
# put r22 in 0x05ec
#******************************************************************
# set msr pow bit to go into sleep mode
sync
mfmsr r5
addis r3, r0, 0x0004
ori r3, r3, 0x0000
or r5, r3, r5
mtmsr r5
isync
# get MSR
# turn on POW bit
# turn on ME bit 19
addis r20, r0, 0x0000
ori r20, r20, 0x0002
stay_here:
addic. r20, r20, -1
bgt cr0, stay_here
# subtract 1 from r20 and set cc
# loop if positive
# restore corrupted registers
lwz r23,0x05e4,r0
F
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