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參數(shù)資料
| 型號： | FX019P |
| 英文描述： | Digitally Controlled Gain Amplifier |
| 中文描述： | 數(shù)控增益放大器 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 58K |
| 代理商： | FX019P |
4
Table 2 Gain Control Word Format
Bit 3
MSB
Bit2
Bit 1
Bit 0
LSB
Stage 1, 2, 3
(0.43dB)
Stage 4
(2.0dB)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
OFF
-3.0
-2.571
-2.143
-1.714
-1.286
-0.857
-0.428
0
0.428
0.857
1.286
1.714
2.143
2.571
3.0
OFF
-14.0dB
-12.0
-10.0
-8.0
-6.0
-4.0
-2.0
0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
t
LLW
Load/Latch Pulse Width
t
LLO
Load/Latch Over Time
t
DS
Data Set-up Time
t
DH
Data Hold Time
t
LLD
Load/Latch Delay
Timing
t
PWH
Serial Clock "High" Pulse Width
t
PWL
Serial Clock "Low" Pulse Width
The gain of each amplifier block (Channel 1 to
Channel 4) in the FX019 is set by a separate 8-bit
data word ( bit 7 to bit 0 ). This 8-bit word, consisting
of 4 Address bits (bit 7 to bit 4) and 4 Gain Control
bits (bit 3 to bit 0), is loaded to the Control Data Input
in serial format using the external data clock.
Data Loading
The 8-bit data word is loaded bit 7 first and bit 0last.
Bit 7 must be a logic “1” to address the chip.
If bit 7 in the word is a logic “0” that 8-bit word will not be
executed. The Chip Select input permits the use of two
devices in a system; To facilitate this, Bit 6 can be either
a logic “0” or “1.” Figure 4 (below) shows the timing
information required to load and operate this device.
Control Data and Timing
Fig.4 Serial Control Data Loading Diagram
Chip
1
Chip
2
Table 1 Address Word Format
Bit 7
MSB
Bit 6
Bit 5
Bit 4
LSB
Channel
Selected
Chip
Select
Chip
Number
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
2
3
4
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
1
2
3
4
1
1
1
1
Data is loaded to the FX019 on the rising edge of the
Serial Clock. Loaded data is executed on the falling
(rising) edge of the Load/Latch (Load/Latch) pulse.
Table 1 shows the format of each 4-bit Address word,
Table 2 shows the format of each Gain Control word
with Figure 4 describing the data loading operation and
timing.
SERIAL DATA CLOCK
t
PWL
t
PWH
t
DS
Loaded Last
Logic ’1’
Loaded
First
BIT 7
BIT 6
BIT 1
BIT 0
t
DH
SERIAL DATA IN
(ONE 8-BIT WORD)
t
LLO
8th
Clock
Pulse
Next
Clock
Pulse
t
LLD
t
LLW
LOAD/LATCH
LOAD/LATCH
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