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參數(shù)資料
| 型號(hào)： | FW804 |
| 英文描述： | PHY IEEE 1394A Four-Cable Transceiver/Arbiter Device |
| 中文描述： | PHY的IEEE 1394A端口四線收發(fā)器/仲裁器裝置 |
| 文件頁(yè)數(shù)： | 7/24頁(yè) |
| 文件大?。?/td> | 398K |
| 代理商： | FW804 |
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Agere Systems Inc.
7
Data Sheet, Rev. 3
June 2001
Four-Cable Transceiver/Arbiter Device
FW804 PHY
IEEE
1394A
Signal Information
(continued)
Table 1. Signal Descriptions
Pin
Signal
*
Type
Name/Description
22
C/LKON
I/O
Bus Manager Capable Input and Link-On Output.
On hardware reset, this pin is
used to set the default value of the contender status indicated during self-ID. The
bit value programming is done by tying the signal through a 10 k
resistor to V
DD
(high, bus manager capable) or to GND (low, not bus manager capable). Using
either the pull-up or pull-down resistor allows the link-on output to override the
input value when necessary.
After hardware reset, this pin is set as an output.
If the LPS is inactive, C/LKON
indicates one of the following events by asserting a 6.114 MHz signal.
1. FW804 receives a link-on packet addressed to this node.
2. Port_event register bit is 1.
3. Any of the Timeout, Pwr_Fail, or Loop register bits are 1 and the Resume_int
register bit is also 1. Once activated, the C/LKON output will continue active until
the LPS becomes active. The PHY also deasserts the C/LKON output when a bus
reset occurs, if the C/LKON is active due solely to the reception of a link-on packet.
Note:
If an interrupt condition exists which would otherwise cause the C/LKON
output to be activated if the LPS were inactive, the C/LKON output will be activated
when the LPS subsequently becomes inactive.
Cable-Not-Active Output.
CNA is asserted high when none of the PHY ports are
receiving an incoming bias voltage. This circuit remains active during the power-
down mode.
Cable Power Status.
CPS is normally connected to the cable power through a
400 k
resistor. This circuit drives an internal comparator that detects the pres-
ence of cable power. This information is maintained in one internal register and is
available to the LLC by way of a register read (see Table 8, Register 0).
Control I/O.
The CTLn signals are bidirectional communications control signals
between the PHY and the LLC. These signals control the passage of information
between the two devices. Bus-keeper circuitry is built into these terminals.
17
CNA
O
27
CPS
I
4
CTL0
I/O
5
CTL1
7, 8, 10,
11, 12, 13,
14, 15
26
D[0:7]
I/O
Data I/O.
The Dn signals are bidirectional and pass data between the PHY and the
LLC. Bus-keeper circuitry is built into these terminals.
/ISO
I
Link Interface Isolation Disable Input (Active-Low).
/ISO controls the operation
of an internal pulse differentiating function used on the PHY-LLC interface signals,
CTLn and Dn, when they operate as outputs. When /ISO is asserted low, the isola-
tion barrier is implemented between PHY and its LLC (as described in Annex J of
IEEE
1394-1995). /ISO is normally tied high to disable isolation differentiation.
Bus-keepers are enabled when /ISO is high (inactive) on CTL, D, and LREQ.
When /ISO is low (active), the bus-keepers are disabled. Please refer to Agere’s
application note AP98-074CMPR for more information on isolation.
* Active-low signals are indicated by “/” at the beginning of signal names, within this document.
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| FW804-09-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:PHY IEEE 1394A Four-Cable Transceiver/Arbiter Device |
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