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參數資料
| 型號： | FT-70U |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | 256K (32768 words 8 bits) SRAM Control Pins: OE and CE |
| 中文描述： | 256K（32768字8位）的SRAM控制引腳：OE和行政長官 |
| 文件頁數： | 6/7頁 |
| 文件大?。?/td> | 49K |
| 代理商： | FT-70U |
No. 6302-6/7
LC35256FM, FT-55U/70U
Notes:1. WE must be held at the high level during the read cycle.
2. Do not apply reverse phase signals to the D
OUT
pins when those pins are in the output state.
3. The time t
WP
is the period when both CE and WE are low. It is defined as the time from the fall of WE to the rise of CE or WE, whichever occurs
first.
4. The time t
CW
is the period when both CE and WE are low. It is defined as the time from the fall of CE to the rise of CE or WE, whichever occurs first.
5. The D
OUT
pins will be in the high-impedance state if any one of the following hold: OE is at the high level, CE is at the high level, or WE is at the low
level.
6. The OE pin must be either held high or held low during the write cycle.
7. D
OUT
has the same phase as the write data during this write cycle.
Parameter
Symbol
Conditions
min
typ
*
max
Unit
Data retention supply voltage
V
DR
V
CE
≥
V
CC
– 0.2 V
2.0
5.5
V
Ta
≤
25°C
Ta
≤
60°C
Ta
≤
70°C
Ta
≤
85°C
0.02
Data retention supply current
I
CCDR
V
CC
= 3.0 V
V
CE
≥
V
CC
– 0.2 V
1.0
μA
2.0
3.5
Chip enable setup time
t
CDR
t
R
0
ns
Chip enable hold time
t
RC
**
ns
Note:
*
Reference values for V
CC
= 3 V, Ta = 25°C.
**
t
RC
: Read cycle time
Data Retention Conditions
at Ta = –40 to +85°C
Data Retention Waveforms
VCC
VCCL
*
VIH
VDR
VCE
GND
VCE
≥
VCC – 0.2 V
tCDR
tR
Data retention mode
Circuit Design Notes
When designing application circuits, always take the following into consideration and design the circuits so that the
absolute maximum ratings are never exceeded.
Supply voltage fluctuations
Sample-to-sample variations in the electrical characteristics of the electronic components used, including
semiconductor devices, resistors, and capacitors.
Ambient temperature
Variations in the input and clock signals
The application of abnormal pulses
Furthermore, be sure to operate this device within the stipulated ranges of all parameters for which an allowable
operating range is specified.
When CMOS IC input pins are left in the open state, through currents may occur in internal circuits to which
intermediate voltage levels are applied, and this can result in incorrect circuit operation. Be sure to handle all unused
input pins as specified in the device documentation.
Note:
*
V
CCL
5 V operation: 4.5 V
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