參數(shù)資料
型號(hào): FST6800WM
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: MSTBO 2,5/ 4 - G1L
中文描述: CBT/FST/QS/5C/B SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24
封裝: 0.300 INCH, MS-013, SOIC-24
文件頁數(shù): 1/5頁
文件大?。?/td> 121K
代理商: FST6800WM
1999 Fairchild Semiconductor Corporation
DS500022
www.fairchildsemi.com
June 1997
Revised December 1999
F
FST6800
10-Bit Bus Switch with Pre-Charged Outputs
General Description
The Fairchild Switch FST6800 provides 10-bits of high-
speed CMOS TTL-compatible bus switching. The low on
resistance of the switch allows inputs to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise. The device precharges
the B Port to a selectable bias voltage (BiasV) to minimize
live insertion noise.
The device is organized as a 10-bit switch with a bus
enable (OE) signal. When OE is LOW, the switch is ON
and Port A is connected to Port B. When OE is HIGH, the
switch is OPEN and the B Port is precharged to BiasV
through an equivalent 10-k
resistor.
Features
I
4
switch connection between two ports.
I
Minimal propagation delay through the switch.
I
Low l
CC
.
I
Zero bounce in flow-through mode.
I
Output precharge to minimize live insertion noise.
I
Control inputs compatible with TTL level.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
Pin Descriptions
Connection Diagram
Truth Table
Order Number
FST6800WM
FST6800QSC
FST6800MTC
Package Number
M24B
MQA24
MTC24
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Name
Description
OE
A
B
Bus Switch Enable
Bus A
Bus B
OE
B
0
–B
9
Function
L
A
0
A
9
Connect
H
BiasV
Precharge
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