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參數(shù)資料
| 型號： | FSHDMI08MTDX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 5/11頁 |
| 文件大小： | 0K |
| 描述： | IC HDMI SWITCH DDC/CEC 56-TSSOP |
| 標準包裝： | 1 |
| 功能： | 開關(guān)，DVI/HDMI |
| 電路： | 3 x 2:1 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 1223 (CN2011-ZH PDF) |
| 其它名稱： | FSHDMI08MTDXDKR |
Micrel, Inc.
SY54017R
March 2008
3
M9999-033108-A
hbwhelp@micrel.com or (408) 955-1690
Pin Description
Pin Number
Pin Name
Pin Function
16,1
4,5
IN0, /IN0
IN1,/IN1
Differential Inputs: These input pairs are the differential signal inputs to the device.
They accept differential signals as small as 100mV (200mVPP). Each input pin
internally terminates with 50
to the VT pin. If the input swing falls below a certain
threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a stable
output by latching the output to its last valid state.
2
3
VT0
VT1
Input Termination Center-Tap: Each side of the differential input pair terminates to a
VT pin. This pin provides a center-tap to a termination network for maximum
interface flexibility. An internal high impedance resistor divider biases VT to allow
input AC coupling. For AC-coupling, bypass VT with a 0.1F low ESR capacitor to
VCC. See “Interface Applications” subsection and Figure 2a.
15
SEL
This single-ended TTL/CMOS compatible input selects the inputs to the multiplexer.
Note that this input is internally connected to a 25k ohm pull-up resistor and will
default to a logic HIGH state if left open.
7
VCC
Positive Power Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to
the VCC pin as possible. Supplies input and core circuitry.
8,13
VCCO
Output Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to the VCCO
pins as possible. Supplies the output buffer.
14
GND,
Exposed pad
Ground: Exposed pad must be connected to a ground plane that is the same
potential as the ground pin.
11,10
Q, /Q
CML Differential Output Pair: Differential buffered copy of the input signal. The
output swing is typically 390mV. See “Interface Applications” subsection for
termination information.
Truth Table
SEL
OUTPUT
0
IN0 Input Selected
1
IN1 Input Selected
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