參數(shù)資料
型號(hào)： FSA9288AUMX
廠商： Fairchild Semiconductor
文件頁(yè)數(shù)： 20/30頁(yè)
文件大?。?/td> 0K
描述： IC USB MULTIMEDIA SWITCH 20-UMLP
標(biāo)準(zhǔn)包裝： 5,000
功能： USB 開(kāi)關(guān)
電路： 3:1
電壓電源： 單電源
電壓 - 電源，單路/雙路(±)： 3 V ~ 4.4 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-UFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 20-UMLP（4x3）
包裝： 帶卷 (TR)
2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A Rev 1.1.0
27
FS
A9
2
80A
—
US
B
Po
rt
Mu
lt
im
edia
Swi
tc
h
,
Fea
turi
n
g
Automatic
Se
lect
a
nd
Ac
ces
s
ory
Detection
11. Layout Guidelines
11.1. PCB Layout Guidelines for High-Speed
USB Signal Integrity
1.
Place FSA9280A as close to the USB controller as
possible. Shorter traces mean less loss, less chance of
picking up stray noise, and may radiate less EMI.
a)
Keep the distance between the USB controller and
the device less than one inch (< 1in).
b)
For best results, this distance should be <18mm.
This keeps it less than one quarter () of the
transmission electrical length.
2.
Use an
impedance calculator to ensure 90 differential
impedance for DP_COM/DM_CON lines.
3.
Select the best transmission line for the application.
a)
For example, for a densely populated board, select
an edge-coupled differential stripline.
4.
Minimize the use of vias and keep HS USB lines on
same plane in the stack.
a)
Vias are an interruption in the impedance of the
transmission line and should be avoided.
b)
Try to avoid routing schemes that generally force
the use of at least two vias: one on each end to get
the signal to and from the surface.
5.
Cross lines, only if necessary, orthogonally to avoid
noise coupling (traces running in parallel couple).
6.
If possible, separate HS USB lines with GND to improve
isolation.
a)
Routing GND, power, or components close to the
transmission
lines
can
create
impedance
discontinuities.
7.
Match transmission line pairs as much as possible to
improve skew performance.
8.
Avoid sharp bends in PCB traces; a chamfer or
rounding is generally preferred.
9.
Place decoupling for power pins as close to the device
as possible.
a)
Use low-ESR capacitors for decoupling if possible.
b)
A tuned PI filter should be used to negate the
effects of switching power supplies and other noise
sources if needed.
11.2. Layout for GSM/TDMA Buzz Reduction
There are two possible mechanisms for TDMA/GSM noise to
negatively impact the FSA9280A device
s performance. The
first is the result of large current draw by the phone
transmitter during active signaling when the transmitter is at
full or almost full power. With the phone transmitter dumping
large amounts of current in the phone GND plane; it is
possible for there to be temporary voltage excursions in the
GND plane if not properly designed. This noise can be
coupled back up through the GND plane into the FSA9280A
device and, although the FSA9280A has very good isolation;
if the GND noise amplitude is large enough, it can result in
noise coupling to the VBUS_IN/MIC pin. The second path for
GSM noise is through electromagnetic coupling onto the
signal lines themselves.
In most cases, the noise introduced as a result of this noise
is on the VBAT and/or GND supply rails. Following are
recommendations for PCB board design that help address
these two sources of TDMA/GSM noise.
1.
Provide a wide, low-impedance GND return path to both
the FSA9280A and to the power amplifier that sources
the phone transmit block.
2.
Provide separate GND connections to PCB GND plane
for each device. Do not share GND return paths
between devices.
3.
Add as large a decoupling capacitor as possible (
1F)
between the VBAT pin and GND to shunt any power
supply noise away from the FSA9280A. Also add
decoupling capacitance at the PA (see the reference
application schematic in Figure 27 for recommended
decoupling capacitor values).
4.
Add 33pF shunt capacitors on any PCB nodes with the
potential to collect radiated energy from the phone
transmitter. At a minimum, add these 33pF capacitors to
the MIC pin (see Figure 27).
5.
Add a series RBAT resistor prior to the decoupling
capacitor on the VBAT pin to attenuate noise prior to
reaching the FSA9280A.
11.3. VBUS_OUT Load Timing Requirements
The FSA9280A includes over-current protection (OCP) used
to protect the FSA9280A and any downstream devices from
a high-current event. In addition, the FSA9280A has an
inrush-limiting feature that helps protect against high-current
transient currents during initial charger FET closure. For
these two reasons, it is recommended that the system
designer delay current draw >250mA from the FSA9280A
VBUS_OUT pin until at least 10ms after VBUS_OUT is valid.
Failure to observe this timing requirement could result in
false OCP triggering and, in some cases, could result in the
FSA9280A staying in OCP Mode until the load is removed
and re-attached.
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