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參數(shù)資料
| 型號： | FSA321UMX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SWITCH MULTIMEDIA 10-UMLP |
| 標準包裝： | 5,000 |
| 功能： | 音頻，USB 開關 |
| 電路： | 1 x DPDT |
| 導通狀態(tài)電阻： | 11 歐姆（USB），2.7 歐姆（音頻） |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 1.8 V ~ 4.3 V |
| 電流 - 電源： | 500µA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-UFQFN |
| 供應商設備封裝： | 10-uMLP（1.4x1.8） |
| 包裝： | 帶卷 (TR) |
Lattice Semiconductor
ispGDX2 Family Data Sheet
3
The sysIO interfaces provide system-level performance and integration. These I/Os support various modes of
LVCMOS/LVTTL and support popular high-speed standard interfaces such as GTL+, PCI-X, HSTL, SSTL, LVDS
and Bus-LVDS. The sysHSI Blocks further extend this capability by providing high speed serial data transfer capa-
bility.
Devices in the family can operate at 3.3V, 2.5V or 1.8V core voltages and can be programmed in-system via an
IEEE 1149.1 interface that is compliant with the IEEE 1532 standard. Voltages required for the I/O buffers are inde-
pendent of the core voltage supply. This further enhances the exibility of this family in system designs.
Typical applications for the ispGDX2 include multi-port multi-processor interfaces, wide data and address bus mul-
tiplexing, programmable control signal routing and programmable bus interfaces. Table 1 shows the members of
the ispGDX2 family and their key features.
Architecture
The ispGDX2 devices consist of GDX Blocks interconnected by a Global Routing Pool (GRP). Signals interface
with the external system via sysIO banks. In addition, each GDX Block is associated with a FIFO and a sysHSI
Block to facilitate the transfer of data on- and off-chip. Figure 1 shows the ispGDX2 block diagram. Each GDX
Block can be individually congured in one of four modes:
Basic (No FIFO or SERDES)
FIFO Only
SERDES Only
SERDES and FIFO
Each sysIO bank has its own I/O power supply and reference voltage. Designers can use any output standard
within a bank that is compatible with the power supply. Any input standard may be used, providing it is compatible
with the reference voltage. The banks are independent.
Global Routing Pool (GRP)
The ispGDX2 architecture is organized into GDX Blocks, which are connected via a Global Routing Pool. The inno-
vative GRP is optimized for routability, exibility and speed. All the signals enter via the GDX Block. The block sup-
plies these either directly or in registered form to the GRP. The GRP routes the signals to different blocks, and
provides separate data and control routing. The data path is optimized to achieve faster speed and routing exibility
for nibble oriented signals. The control routing is optimized to provide high-speed bit oriented routing of control sig-
nals.
There are some restrictions on the allocation of pins for optimal bus routing. These restrictions are considered by
the software in the allocation of pins.
GDX Block
The blocks are organized in a “block” (nibble) manner, with each GDX Block providing data ow and control logic
for 16 I/O buffers. The data ow is organized as four nibbles, each nibble containing four Multiplexer Register
Blocks (MRBs). Data for the MRBs is provided from 64 lines from the GRP. Figure 2 illustrates the groups of signals
going into and out of a GDX Block.
Control signals for the MRBs are provided from the Control Array. The Control Array receives the 32 signals from
the GRP and generates 16 control signals: eight MUX Select, four Clock/Clock Enable, two Set/Reset and two Out-
put Enable. Each nibble is controlled via two MUX select signals. The remaining control signals go to all the MRBs.
Besides the control signals from the Control Array, the following global signals are available to the MRBs in each
GDX Block: four Clock/Clock Enable, one reset/preset, one power-on reset, two of four MUX select (two of two in
64 I/O), four Output Enable (two in 64 I/O) and Test Out Enable (TOE).
SELECT
DEVICES
DISCONTINUED
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| FSA321UMX_F113 | 功能描述:多路器開關 IC Multimedia & USB2 Hi-Speed & Aud Swtch RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 開關數(shù)量:4 開啟電阻（最大值）:7 Ohms 開啟時間（最大值）: 關閉時間（最大值）: 傳播延遲時間:0.25 ns 工作電源電壓:2.3 V to 3.6 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UQFN-16 |
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